Displaying 6 results from an estimated 6 matches for "acquirerelease".
2011 Sep 17
2
[LLVMdev] Invalid STOREATOMIC Record
The second equality here: (in lib/Bitcode/Reader/BitcodeReader.cpp)
AtomicOrdering Ordering = GetDecodedOrdering(Record[OpNum+2]);
if (Ordering == NotAtomic || Ordering == Release ||
Ordering == AcquireRelease)
return Error("Invalid STOREATOMIC record");
Is failing on this assembly, which was generated by Clang:
store atomic i32 0, i32* @mutex release, align 4
Is this a typo or is there some reason why this assembly is invalid?
Thanks,
- pdox
2011 Sep 17
0
[LLVMdev] Invalid STOREATOMIC Record
...11 at 1:00 PM, David Meyer <pdox at google.com> wrote:
> The second equality here: (in lib/Bitcode/Reader/BitcodeReader.cpp)
>
> AtomicOrdering Ordering = GetDecodedOrdering(Record[OpNum+2]);
> if (Ordering == NotAtomic || Ordering == Release ||
> Ordering == AcquireRelease)
> return Error("Invalid STOREATOMIC record");
>
> Is failing on this assembly, which was generated by Clang:
>
> store atomic i32 0, i32* @mutex release, align 4
>
> Is this a typo or is there some reason why this assembly is invalid?
Typo; that should read...
2011 Aug 23
1
[LLVMdev] LLVM Concurrency and Undef
...ore the other, and at least one of them is
> not atomic, r2==undef. The seq_cst ordering a, c, d, e is consistent
> with the observable results. That's true whether printing r2 prints 1,
> 2, or 47 since undef can be observed as any value.
My confusion is the difference between SC and AcquireRelease. The text says
...
SequentiallyConsistent
SequentiallyConsistent (seq_cst in IR) provides Acquire semantics for
loads and Release semantics for stores. Additionally, it guarantees
that a total ordering exists between all SequentiallyConsistent
operations.
...
Here, what does the total ordering m...
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...t is, syntactically I propose:
+ No comma between the two
+ Both operands are required, even if "failure" is the natural pair
of "success"
Semantically, I would like to enforce the constraints in the standards:
+ failure <= success
+ failure != Release
+ failure != AcquireRelease.
Before the DAG, I suggest completely removing getOrdering from
CmpXchgInst, in favour of getSuccessOrdering and getFailureOrdering to
avoid errors. In the DAG, getOrdering would still exist and return the
success ordering, which I believe would make existing targets
conservatively correct. Atomic...
2011 Aug 22
0
[LLVMdev] LLVM Concurrency and Undef
On Mon, Aug 22, 2011 at 4:20 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote:
> On Mon, Aug 22, 2011 at 6:49 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>> On Mon, Aug 22, 2011 at 3:40 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote:
>>> On Mon, Aug 22, 2011 at 6:08 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>>>> On
2011 Aug 22
2
[LLVMdev] LLVM Concurrency and Undef
On Mon, Aug 22, 2011 at 6:49 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Mon, Aug 22, 2011 at 3:40 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote:
>> On Mon, Aug 22, 2011 at 6:08 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
>>> On Mon, Aug 22, 2011 at 2:49 PM, Santosh Nagarakatte
>>> <santosh.nagarakatte at gmail.com>