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icc_a
2018 Apr 10
1
How to finalize instruction lowering after register allocation.
...he FPU instruction format has a 2 bits operand indicating which units are involved: none, only UnitA, only UnitB, and the SIMD version UnitA and UnitB.
The SIMD version of a FPU instruction operates on registers with the same ID of both banks.
For examples:
FADD A R1, R2; // => ACC_A = RegisterA_1 + RegisterA_1
FADD B R5, R6; // => ACC_B = RegisterB_5 + RegisterB_6
FADD AB R7, R8; // => ACC_A = RegisterA_7 + RegisterA_8 and ACC_B = RegisterB_7 + RegisterB_8
>From a machine registers definition point of view, I've first defined...