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Hi, I'm having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> =

Good day! I create diagram of encoder process. Using it i create implementation of encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing stages? Here is blog http://developer-fpga.blogspot.com/ Here is picture of encoding stage 1 https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg Here is picture of encoding stage 2

- Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr -- Aur?lien Zanelli Parrot SA 174, quai de Jemmapes 75010 Paris France -------------- next part -------------- diff --git

Please ignore my previous mail and patch, there is a new version :). Patch changes are: - Use MAC16_16 macros instead of (sum += a*b) and unroll a loop by 2. It increase performance when using optimized macros (ex: ARMv5E). A possible side effect of loop unroll is that i don't check for odd length here. - Add NEON version of FIR filter and autocorr - Add a section in autoconf in order to

Package: logcheck Version: 1.2.63 Severity: minor Tags: patch Hi, There was recently a modification to filter acpid stuffs. But there are still things not filtered by logcheck. When I unplugg, then plug back my battery, I get following notifications: System Events =-=-=-=-=-=-= Nov 8 21:41:31 morpork acpid: received event "ac_adapter AC0 00000080 00000000" Nov 8 21:41:31 morpork

---------- Forwarded message ---------- From: digital design <developer.fpga at gmail.com> Date: 21 March 2011 13:38 Subject: Re: [theora] alghorithm of working encoder in libtheora To: bens at alum.mit.edu Cc: Reply-All at xiph.org On 18 March 2011 23:15, Benjamin M. Schwartz <bmschwar at fas.harvard.edu>wrote: > On 03/18/2011 01:44 PM, digital design wrote: > > Now i

Hello Jean-Marc, > Got any luck with the Blackfin stuff? One thing I forgot mentioning that > would probably help a lot in narrowing down the bug is to simply disable > assembly functions one by one and see which one breaks Speex. sorry that I didn't reply for some days. Unfortunately I had some other serious problems with my software which are not related to Speex. I hope to solve

Hi, I get strange code when using regalloc=greedy. A value spill is redundant and cleared, as another spill of same value is inserted. The former spill is however not NOP:ed, but KILL:ed, thus the operands get a kill status. The code becomes: %vreg301<def> = mv32Imm 200000000, pred:0, pred:%noreg, %CCReg<imp-def,dead>, %ac0<imp-use>, %ac1<imp-use>; aN32_0_7:%vreg301

Hi Bernhard, It seems like I messed up somewhere in the lpc code. However, it seems like your patch is also removing some code, which is probably why you see small differences between your asm version and the fixed point. I don't have my setup working at the moment, but could you test the following patch: Index: lpc_bfin.h ===================================================================

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Hello Jean-Marc, I disabled the Blackfin optimization functions one by one and found the error in libspeex/lpc_bfin.h in the autocorrelation computation. Compared to the fixed-point-variant of that function (from lpc.c), the blackfin-code produces correct values except for the zero offset value. Additionally, the loop after the ASM-code assigned values (ac32) wrong to the functions

Hy people, where could this be coming from? rsync: send_files failed to open "Alfredo Polti SA/wz_ALFREDO_POLTI_SA.ac0" (in Winway_z-32): Device or resource busy (16) rsync: send_files failed to open "Alfredo Polti SA/wz_ALFREDO_POLTI_SA.ac3" (in Winway_z-32): Device or resource busy (16) rsync error: some files/attrs were not transferred (see previous errors) (code 23) at

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Hi, I am trying to use two products that use SysLinux and finally realised the SysLinux is the cause of my woes. I'm trying to use Freesco and IPCop. IPCop version 1.3 used a different boot loader to 1.4 which uses SysLinux. I have been through numerous trials and tribulations in trying to get Freesco to work but eventually gave up and went with IPCop. I kept getting the "Boot

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Thank, Timothy! I add this stages. About RLE: I have one more unresolved stage. Mike Melanson wrote in "VP3 Bitstream Format..." about RLE using: "* Zigzag Ordering: After transforming and quantizing a block of samples, the samples are not in an optimal order for run length encoding. Zigzag ordering rearranges the samples to put more zeros between non-zero samples." If we pass

http://bugs.freedesktop.org/show_bug.cgi?id=27064 Summary: Nouveau fails to start X. This is a Nvidia G210m, the laptop is an asus UL50vt Product: xorg Version: 7.5 Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: critical Priority: medium Component: Driver/nouveau

hi there ;-) can you help ? ouer network has gone unreasonly slow newerdays, i?m nearly shure its no virus or shit.... i?d used tcpdump to see whats going on and found these errormessages ouer network is quite small, the linuxserver(samba), some windoofclients and the plotter_pc ( this one runs as a MSdosclient and searches a pathstructure for new files) what is this SNAP length ??? and