search for: ac0

...;m having an issue with subregisters on my target. With a pseudo that writes to a 32 bit reg: %vreg20<def> = toHi16_low0_pseudo %vreg2; reg32:%vreg20 hi16:%vreg2 expands to %vreg2<def> = COPY %a2h; hi16:%vreg2 %vreg43<def> = mov 0, pred:0, pred:%noreg, %ac0<imp-use>, %ac1<imp-use>; lo16:%vreg43 %vreg20<def> = REG_SEQUENCE %vreg2, hi16, %vreg43, lo16; reg32:%vreg20 hi16:%vreg2 lo16:%vreg43 Becomes 16L %vreg20:hi16<def,undef> = COPY %a2h<kill>, %vreg20<imp-def>; reg32:%vreg20 368L %vre...

Good day! I create diagram of encoder process. Using it i create implementation of encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing stages? Here is blog http://developer-fpga.blogspot.com/ Here is picture of encoding stage 1 https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg Here is picture of encoding stage 2

...t opus_val32 *x, } } +#ifndef OVERRIDE_CELT_AUTOCORR void _celt_autocorr( const opus_val16 *x, /* in: [0...n-1] samples x */ opus_val32 *ac, /* out: [0...lag-1] ac values */ @@ -163,8 +170,12 @@ void _celt_autocorr( { opus_val32 ac0=0; int shift; - for(i=0;i<n;i++) + int n2 = n>>1; + for(i=0;i<n2;i++) + { ac0 += SHR32(MULT16_16(xx[i],xx[i]),9); + ac0 += SHR32(MULT16_16(xx[n2+i],xx[n2+i]),9); + } ac0 += 1+n; shift = celt_ilog2(ac0)-30+10; @@ -176,7 +1...

...t opus_val32 *x, } } +#ifndef OVERRIDE_CELT_AUTOCORR void _celt_autocorr( const opus_val16 *x, /* in: [0...n-1] samples x */ opus_val32 *ac, /* out: [0...lag-1] ac values */ @@ -163,8 +170,12 @@ void _celt_autocorr( { opus_val32 ac0=0; int shift; - for(i=0;i<n;i++) + int n2 = n>>1; + for(i=0;i<n2;i++) + { ac0 += SHR32(MULT16_16(xx[i],xx[i]),9); + ac0 += SHR32(MULT16_16(xx[n2+i],xx[n2+i]),9); + } ac0 += 1+n; shift = celt_ilog2(ac0)-30+10; @@ -176,7 +1...

...inor Tags: patch Hi, There was recently a modification to filter acpid stuffs. But there are still things not filtered by logcheck. When I unplugg, then plug back my battery, I get following notifications: System Events =-=-=-=-=-=-= Nov 8 21:41:31 morpork acpid: received event "ac_adapter AC0 00000080 00000000" Nov 8 21:41:31 morpork acpid: completed event "ac_adapter AC0 00000080 00000000" Nov 8 21:41:31 morpork acpid: received event "processor CPU1 00000080 00000004" Nov 8 21:41:31 morpork acpid: completed event "processor CPU1 00000080 00000004"...

...-------------------+ ADDR | VALUE | +----+---------------------------------+ N | DC results after Huffman blocks | N+1 | DC results after Huffman blocks | .. | ... | N+m | DC results after Huffman blocks | 3.2 the same (like 3.1) for all AC0...AC62 Results in buffer memory (DDR2) after Huffman DDR2: +----+----------------------------------+ ADDR | VALUE | +----+----------------------------------+ N | DC results after Huffman blocks | .. | ... | M | AC0 results after Huf...

Hello Jean-Marc, > Got any luck with the Blackfin stuff? One thing I forgot mentioning that > would probably help a lot in narrowing down the bug is to simply disable > assembly functions one by one and see which one breaks Speex. sorry that I didn't reply for some days. Unfortunately I had some other serious problems with my software which are not related to Speex. I hope to solve

...c=greedy. A value spill is redundant and cleared, as another spill of same value is inserted. The former spill is however not NOP:ed, but KILL:ed, thus the operands get a kill status. The code becomes: %vreg301<def> = mv32Imm 200000000, pred:0, pred:%noreg, %CCReg<imp-def,dead>, %ac0<imp-use>, %ac1<imp-use>; aN32_0_7:%vreg301 Store32FI %vreg301, <fi#93>, pred:0, pred:%noreg, %CCReg<imp-def>; mem:ST4[FixedStack93] aN32_0_7:%vreg301 KILL %vreg301, <fi#93>, 0, %noreg, %CCReg<imp-def>; mem:ST4[FixedStack93] aN32_0_7:%vreg301 %a0_32&lt...

...nd the fixed point. I don't have my setup working at the moment, but could you test the following patch: Index: lpc_bfin.h =================================================================== --- lpc_bfin.h (r?vision 10333) +++ lpc_bfin.h (copie de travail) @@ -47,7 +47,7 @@ spx_word32_t ac0=1; spx_word32_t ac32[11], *ac32top; int shift, ac_shift; - ac32top = ac32+10; + ac32top = ac32+lag-1; int lag_1, N_lag; int nshift; lag_1 = lag-1; Let me know if it works. Jean-Marc Le mercredi 09 novembre 2005 ? 14:02 +0100, Bernhard Gerlach a ?crit : > Hello Jean-Ma...

...CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: Add back PLL lock test Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 1 - drm/nouveau/nvk...

...CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: add back PLL lock test v3: add restoring original value after PLL lock test Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/n...

...CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. Tested with GF119 NVS 310. Signed-off-by: Mark Menzynski <mmenzyns at redhat.com> --- drm/nouveau/nvkm/subdev/clk/gf100.c | 8 -------- drm/nouve...

...putation. Compared to the fixed-point-variant of that function (from lpc.c), the blackfin-code produces correct values except for the zero offset value. Additionally, the loop after the ASM-code assigned values (ac32) wrong to the functions output structure (ac). I added a loop to compute ac0-value correctly and another loop, that moves ac32- values to ac. I checked my code with debug printf's comparing Blackfin-ASM-computed values against fixed-point-variant values and found the values to be generally the equal. Some Blackfin-ASM-values differ slightly from fixed-point-valu...

Hy people, where could this be coming from? rsync: send_files failed to open "Alfredo Polti SA/wz_ALFREDO_POLTI_SA.ac0" (in Winway_z-32): Device or resource busy (16) rsync: send_files failed to open "Alfredo Polti SA/wz_ALFREDO_POLTI_SA.ac3" (in Winway_z-32): Device or resource busy (16) rsync error: some files/attrs were not transferred (see previous errors) (code 23) at main.c(1524) [generator=3.0...

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Hi, I am trying to use two products that use SysLinux and finally realised the SysLinux is the cause of my woes. I'm trying to use Freesco and IPCop. IPCop version 1.3 used a different boot loader to 1.4 which uses SysLinux. I have been through numerous trials and tribulations in trying to get Freesco to work but eventually gave up and went with IPCop. I kept getting the "Boot

...CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10: lookup -ac0 0x137000 0x10 PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 } Also, disabling this bit on other CLKs doesn't seem to break anything. v2: add back PLL lock test v3: add restoring original value after PLL lock test v4: read the bit with nvkm_mask Signed-off-by: Mark Menzynski <mmenz...

...an optimal order for run length encoding. Zigzag ordering rearranges the samples to put more zeros between non-zero samples." If we pass zigzaged DCT coeffs of 1 block throw RLE, how after this stage i can separately write different AC for its AC-plane? For example after zig-zag we have this: AC0 =1 AC(1..61) =0 AC62 =1 after RLE we have: (0,1)(61,1) How add zero-ACs coeff to AC(1..61) planes? Or i skip them in this planes and add store only non-zero coeff to plabes? Thanks P.S. please give me more critique. More critique - better implementation On 22 March 2011 22:00, <theora-dev-requ...

...Name unavailable] (20091214/dswexec-445) [ 6.639668] ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0.VGA_._DSM] (Node ffff88013fa5d120), AE_AML_OPERAND_TYPE [ 6.639745] ACPI Error (psparse-0537): Method parse/execution failed [\_SB_.PCI0.P0P1.VGA_._DSM] (Node ffff88013fa5eac0), AE_AML_OPERAND_TYPE [ 6.639803] [drm] nouveau 0000:01:00.0: failed to evaluate _DSM: 12291 [ 6.640552] [drm] nouveau 0000:01:00.0: Detected an NV50 generation card (0x0a8a00a2) [ 6.642081] [drm] nouveau 0000:01:00.0: Attempting to load BIOS image from PRAMIN [ 6.642101] [drm] nouveau...

..... [A80] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [A90] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AA0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AB0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AC0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AD0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AE0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [AF0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ........ ........ [B00] 00...