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...0 September 2019 20:50 To: David Tellenbach <David.Tellenbach at arm.com> Cc: paul.robinson at sony.com <paul.robinson at sony.com>; llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>; nd <nd at arm.com>; Tim Northover <tnorthover at apple.com>; Ahmed Bougacha <abougacha at apple.com> Subject: Re: [llvm-dev] [AArch64] Generated assembly differs depending on whether debug information is generated or not Hi David, Thanks for looking into this. It seems like D68076 might not address the underlying issue here (e.g. it probably doesn't improve the situation fo...

Hi Paul, thanks for your comments. This is PR37240 (https://bugs.llvm.org/show_bug.cgi?id=37240). I suspect this problem affects all targets; your patch D68076 would address it only for AArch64. Although I would suggest you do some careful measurements to determine the runtime performance effect, to decide whether this is acceptable. Yes, in principle the problem that instruction scheduling is

Awesome start. Back when I did a similar project at HP/NonStop, the class of optimizations we turned off for our O1 (Og equivalent) tended to be those that reordered code or otherwise messed with the CFG. In fact one of our metrics was: - The set of breakpoint locations available at Og should be the same as those available at O0. This is pretty easy to measure. It can mean either turning

Hi Ulrich, I am interested in knowing if the current proposals also take into account the FP_CONTRACT pragma and the ability to implement options that imply a specific value for the FLT_EVAL_METHOD macro. Additionally, I am not aware of the IR being able to represent the potentially deferred loss of precision that the C language semantics provide; in particular, applying such semantics to the

Hi All, I’ve been thinking about both O1 and Og optimization levels and have a proposal for an improved O1 that I think overlaps in functionality with our desires for Og. The design goal is to rewrite the O1 optimization and code generation pipeline to include the set of optimizations that minimizes build and test time while retaining our ability to debug. This isn’t to minimize efforts around

Hello, at the recent EuroLLVM developer meeting in Bristol I held a BoF session on the topic "Towards implementing #pragma STDC FENV_ACCESS". I've also had a number of follow-on discussions both on-site in Bristol and online since. This post is intended as a summary of my current understanding set of requirements and implementation details covering the overall topic. I'm