Displaying 6 results from an estimated 6 matches for "abcinst".
2019 Sep 27
2
Maybe a TableGen bug?
Hi,
Here's llvm-tblgen -print-records message:
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0,
0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4},
roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0,...
2019 Aug 27
2
TargetRegisterInfo::getCommonSubClass bug, perhaps.
Hi,
ABCRegister.td :
def SGPR32 : RegisterClass<"ABC", [i32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
===== Instruction selection ends:
...
t8: i32 = ADDrr t37, t32
2019 Nov 20
4
Tablegen PAT limitation?
...diction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32&am...
2019 Nov 21
2
Tablegen PAT limitation?
...diction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32&a...
2019 Nov 22
2
Tablegen PAT limitation?
...diction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32&a...
2019 Nov 25
2
Tablegen PAT limitation?
...diction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
vtInt: (vt:{ *:[Other] })
UNREACHABLE executed at /home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!
def LOADbos { // Instruction ABCInst ABCInstMMEMrr
field bits<32> Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32&a...