search for: aarch64registerinfo

...Daniel Sanders 写道: >>>> >>>> Hi Leslie, >>>> >>>> There should be a definition of GPR8RegClassID in >>>> $build_dir/lib/Target/AVR/AVRGenRegisterInfo.inc which should be included by >>>> AVRRegisterInfo.h. AArch64 includes its AArch64RegisterInfo.h in >>>> AArch64InstructionSelector.cpp but it seems that ARM gets it indirectly when >>>> it includes ARMSubtarget.h. It looks like you need to add '#include >>>> "AVRRegisterInfo.h"' to AVRInstructionSelector.h. >>>> >>>&...

Hi, In the runtime system for GHC Haskell, the stack pointer register is not the same as the one defined by the operating system ABI, and it's difficult for GHC to change that. Following the example of CoreCLR in LLVM, it seems one way to remedy this situation is to define a new ABI (i.e., a new llvm::Triple::EnvironmentType ) and modify the code generator as-needed to respect to our ABI,

Hi, How can I reserve an ARM register for only a part of the code? Example: lets say I have 3 functions, A(), B() and C(). I want to prohibit compiler from using a register (lets say X9 in ARM 64) in function C() only. I think that by AArch64RegisterInfo::getReservedRegs function, a register can be reserved for the whole program. But, I need to reserve for only part of the code. Can I implement a custom #pragma to do it? Thanks and Best Nisal

...arget/PowerPC/MCTargetDesc/Release+Asserts/PPCMCTargetDesc.o differ: byte 132907, line 258 ./lib/Target/AArch64/Release+Asserts/AArch64ISelDAGToDAG.o ../../recurse2be/build/./lib/Target/AArch64/Release+Asserts/AArch64ISelDAGToDAG.o differ: byte 223462, line 2183 ./lib/Target/AArch64/Release+Asserts/AArch64RegisterInfo.o ../../recurse2be/build/./lib/Target/AArch64/Release+Asserts/AArch64RegisterInfo.o differ: byte 20886, line 17 ./lib/Target/AArch64/InstPrinter/Release+Asserts/AArch64InstPrinter.o ../../recurse2be/build/./lib/Target/AArch64/InstPrinter/Release+Asserts/AArch64InstPrinter.o differ: byte 332540, lin...

...ew class StackOffset (https://reviews.llvm.org/D88982). AArch64 uses Stack-IDs to keep fixed- and scalable types apart, but AArch64FrameLowering finally allocates them together in the regular stack frame. StackOffset is returned by e.g. `getFrameIndexReference`, and is used in AArch64FrameLowering/AArch64RegisterInfo to calculate and resolve frame offsets. What works for scalable vectors today? ====================================== Today AArch64 SVE/SVE2 is probably the target with the most complete support, although recently Roger Ferrer also shared a proposal on adding codegen for the RISCV V extension (h...