search for: aarch64loadstoreoptim

Hi All, I have made some changes in AArch64LoadStoreOptimizer.cpp file and with check-llvm all tests are passing successfully. But in llvm-test suite some tests are failing, like consumer-typeset tests are failing. Now I want to debug with 'consumer-typeset' exe from SANDBOX. But it is release build. How can I debug this issue in this case and h...

...virtual register, which would arguably be a bug already. We have encountered several potential uses for this bit. For example, the MachineCopyPropagation changes I have been working on to forward register COPYs would likely be greatly simplified if this bit were available. Other passes, like AArch64LoadStoreOptimizer, which run post-RA so as not to overly-restrict the register allocator, could be made to catch more cases if renaming of load instructions could be done safely. -- Geoff Berry Employee of Qualcomm Datacenter Technologies, Inc. Qualcomm Datacenter Technologies, Inc. as an affiliate of Qua...

Ok, thank you, I will implement it then. As far as I see this optimization should be done in AArch64LoadStoreOptimizer, is it right? From: Eli Friedman [mailto:efriedma at quicinc.com] Sent: Thursday, November 21, 2019 11:55 PM To: Kosov Pavel <kosov.pavel at huawei.com>; LLVM Dev <llvm-dev at lists.llvm.org> Subject: RE: [llvm-dev] [ARM] Peephole optimization ( instructions tst + add ) That tran...

...arguably be a bug already. > > > > We have encountered several potential uses for this bit. For example, > the MachineCopyPropagation changes I have been working on to forward > register COPYs would likely be greatly simplified if this bit were > available. Other passes, like AArch64LoadStoreOptimizer, which run post-RA > so as not to overly-restrict the register allocator, could be made to catch > more cases if renaming of load instructions could be done safely. > > > > -- > > Geoff Berry > > Employee of Qualcomm Datacenter Technologies, Inc. > > Qualcomm...

...the second, in the middle of things, you could try pattern matching in EmitTest() or LowerToBT(). I've tried this and it doesn't work since it needs to reach outside of a Selection DAG. Doesn't work. Can't work. Thirdly, it's been suggested to use a peephole pass and to look at AArch64LoadStoreOptimizer.cpp. This also doesn't work for pretty much the same reason. Moreover, this is after register allocation so even for the limited situations where it can work, it leaves allocated but unutilized registers. Doesn't work. In fact, I'd suggest the Arm backend adopt my approach. So fir...

Hello! I noticed that in some cases clang generates sequence of AND+TST instructions: For example: AND x3, x2, x1 TST x2, x1 I think these instructions should be merged to one: ANDS x3, x2, x1 ( because TST <Xn>, <Xm> is alias for ANDS XZR, <Xn>, <Xm> -

Hi Renato, > > I'm trying to add pseudo 64-bit load and store instructions for AArch64, which > > should have latencies set to "1" while being otherwise exactly the same as > > normal load and store instructions. > > Can I ask why would you need that? This is the only way I found to stop Machine Instruction Scheduler from reordering load and store