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Hi Tim, >That C++ function is probably what looks for an FrameIndex node and >has been taught that it can be folded into the load. How do you teach a function that a node can be folded into an instruction? ________________________________ From: Tim Northover <t.p.northover at gmail.com> Sent: Monday, January 21, 2019 11:52 PM To: Josh Sharp Cc: via llvm-dev Subject: Re: [llvm-dev]

On Tue, Jun 25, 2019 at 9:59 AM Tim Northover <t.p.northover at gmail.com> wrote: > On Tue, 25 Jun 2019 at 06:26, Gleb Popov via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > >> While the store is being selected LLVM will just treat the value being > >> stored as a generic pointer-width integer unless you have written a > >> specific pattern for

.../InstPrinter/Release+Asserts/PPCInstPrinter.o differ: byte 40870, line 25 ./lib/Target/PowerPC/MCTargetDesc/Release+Asserts/PPCMCTargetDesc.o ../../recurse2be/build/./lib/Target/PowerPC/MCTargetDesc/Release+Asserts/PPCMCTargetDesc.o differ: byte 132907, line 258 ./lib/Target/AArch64/Release+Asserts/AArch64ISelDAGToDAG.o ../../recurse2be/build/./lib/Target/AArch64/Release+Asserts/AArch64ISelDAGToDAG.o differ: byte 223462, line 2183 ./lib/Target/AArch64/Release+Asserts/AArch64RegisterInfo.o ../../recurse2be/build/./lib/Target/AArch64/Release+Asserts/AArch64RegisterInfo.o differ: byte 20886, line 17 ./lib/Target/AA...

...d up with store %r1, [1] and handle it in my CPU emulator accordingly. So, instead of matching that FrameIndex in store, I really want to emit a load first and then use a register in the store instruction. Can you, please, advise me how to implement that? See for example > lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2916. > > Cheers. > > Tim. > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190626/0b6684d8/attachment.html>