search for: aarch64instrformats

Displaying 2 results from an estimated 2 matches for "aarch64instrformats".

2015 Sep 14
2
TableGen MCInstrDesc Instruction Size Zero
Dear all, I am trying to write an AsmParser and a CodeEmitter for simple ADD instruction. Here is what I have in the TestGenInstrInfo.td: *extern const MCInstrDesc TestInsts[] = {...{ 23, 3, 1, 0, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo13, 0, nullptr }, // Inst #23 = ADD8_rr...}* I parse the instruction successfully but I am not sure what I did wrong that the Size (as you can see in
2020 Sep 15
2
[EXTERNAL] Re: Simulation of load-store forwarding with MI scheduler on AArch64
Thanks for prompt response, Andy This will work for cases when address is not modified. However this doesn’t seem to work for pre/post increment load stores. Consider data to address forwarding: $x0 = ldr x0, [x1] $x0, $x2 = ldr x2, [x0, 16]! The second instruction will have it’s own latency for address modification ($x0 register). So I don’t see how we can use ReadAdr stuff here. May be