Displaying 4 results from an estimated 4 matches for "aarch64geninstrinfo".
2017 Sep 22
2
SchedClasses
...microops 65535
I would have assumed that the microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong?
Cheers,
Tom
#define GET_REGINFO_ENUM
#include "AArch64GenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "AArch64GenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "AArch64GenSubtargetInfo.inc"
#include "llvm/MC/MCSchedule.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/SubtargetF...
2017 Sep 29
0
SchedClasses
...e microops are less than 20. The ThunderX2 has a detailed cost model for LSE. Could somebody tell me what I am doing wrong?
>
> Cheers,
> Tom
>
> #define GET_REGINFO_ENUM
> #include "AArch64GenRegisterInfo.inc"
>
> #define GET_INSTRINFO_ENUM
> #include "AArch64GenInstrInfo.inc"
>
> #define GET_SUBTARGETINFO_ENUM
> #include "AArch64GenSubtargetInfo.inc"
>
> #include "llvm/MC/MCSchedule.h"
> #include "llvm/MC/MCRegisterInfo.h"
> #include "llvm/MC/MCInstrDesc.h"
> #include "llvm/MC/MCInstrInfo.h...
2017 Sep 30
1
SchedClasses
...t; On Sep 22, 2017, at 10:34 AM, Thorsten Schütt via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> >
>
> >
> > #define GET_REGINFO_ENUM
> > #include "AArch64GenRegisterInfo.inc"
> >
> > #define GET_INSTRINFO_ENUM
> > #include "AArch64GenInstrInfo.inc"
> >
> > #define GET_SUBTARGETINFO_ENUM
> > #include "AArch64GenSubtargetInfo.inc"
> >
> > #include "llvm/MC/MCSchedule.h"
> > #include "llvm/MC/MCRegisterInfo.h"
> > #include "llvm/MC/MCInstrDesc.h"
> >...
2018 May 10
2
[RFC] MC support for variant scheduling classes.
...the definition of IsGPRZero using a TIIPredicate.
```
def IsGPRZero : TIIPredicate<"AArch64", "isGPRZero",
AnyOfMCPredicates<[CheckMOVZ, CheckANDW, CheckANDX, CheckCOPY]>>;
```
This is how the InstructionInfoEmitter expands the method in the tablegen'd
class AArch64GenInstrInfo:
```
static bool isGPRZero(const MachineInstr &MI) {
return (
(
(
MI.getOpcode() == AArch64::MOVZWi
|| MI.getOpcode() == AArch64::MOVZXi
)
&& MI.getNumOperands() == 3
&& MI.getOperand(1).isImm()
&&...