Displaying 5 results from an estimated 5 matches for "aarch64addresstypepromotion".
2014 Jun 27
3
[LLVMdev] Contributing the Apple ARM64 compiler backend
AArch64AddressTypePromotion.cpp does a fair bit of work to help make these things work out well. It could probably be generalized for non-AArch64 targets as per the comment in the file header.
> On Jun 26, 2014, at 10:42 AM, Sanjay Patel <spatel at rotateright.com> wrote:
>
> Cool HW trick. :)
> Are those...
2016 Feb 29
2
[GSoC 2016] Code Generation Improvements task
...mostly target independent so to generalize them code
needs to be wrap in MachineFunction pass and then use it as required.
And if already not done , Merge Set of SSA based CFG can be computed at
time of SSA generation. This can improve performance of Ramakrishna’s
algorithm.
2. lib/Target/AArch64/AArch64AddressTypePromotion.cpp
As far as I understand this pass promotes sign exertion for 32 bit integer
( address) and performs calculation on 64 bit number thus processes need
not switch execution mode to 32 bit.
Some other platforms such as MIPS, NVPTX, Sparc can be benefited by such
optimization because MIPS64 supports...
2016 Mar 01
2
[GSoC 2016] Code Generation Improvements task
Hi Vivek,
(Mostly responding with AArch64 hints, though anything I happen to
know from elsewhere too).
On 29 February 2016 at 13:00, vivek pandya via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> 2. lib/Target/AArch64/AArch64AddressTypePromotion.cpp
> As far as I understand this pass promotes sign exertion for 32 bit integer (
> address) and performs calculation on 64 bit number thus processes need not
> switch execution mode to 32 bit.
Switching execution mode isn't an option on AArch64 (it can only
happen with OS support an...
2016 Mar 01
0
[GSoC 2016] Code Generation Improvements task
...hover at gmail.com>
wrote:
> Hi Vivek,
>
> (Mostly responding with AArch64 hints, though anything I happen to
> know from elsewhere too).
>
> On 29 February 2016 at 13:00, vivek pandya via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > 2. lib/Target/AArch64/AArch64AddressTypePromotion.cpp
> > As far as I understand this pass promotes sign exertion for 32 bit
> integer (
> > address) and performs calculation on 64 bit number thus processes need
> not
> > switch execution mode to 32 bit.
>
> Switching execution mode isn't an option on AArch64 (it...
2014 Jun 26
2
[LLVMdev] Contributing the Apple ARM64 compiler backend
Hi Sanjay,
The behaviour I’m talking about I’ve actually pinned down to CodeGenPrepare not working too well with ISA’s that don’t have a good scaled load. I have a patch to fix it that is going through performance testing now.
Your testcase seems specific to x86 – for aarch64 we get the rather spiffy:
_Z3fooPii: // @_Z3fooPii
// BB#0: