Displaying 2 results from an estimated 2 matches for "aa23d50d".
2011 Jul 19
0
[LLVMdev] Custom lowering of load with extension
On Mon, Jul 18, 2011 at 6:35 PM, Damien Vincent <damien.llvm at gmail.com> wrote:
>
> Hi,
>
> The target I am working on does not support i8 loading: it supports only 32
> bit aligned loads.
> I had to custom lower i8 load so that only i32 loads are generated.
>
> My issue is the following:
> In a very specific case, the lowering stage generates the following
2011 Jul 19
2
[LLVMdev] Custom lowering of load with extension
Hi,
The target I am working on does not support i8 loading: it supports only 32
bit aligned loads.
I had to custom lower i8 load so that only i32 loads are generated.
My issue is the following:
In a very specific case, the lowering stage generates the following pattern
where the load is a i32 load:
(and (load x), 255)
This pattern is somehow converted by the DAG combiner back to:
(zextload x,