Displaying 3 results from an estimated 3 matches for "a9_agu".
2011 Oct 07
1
[LLVMdev] Multiple-Pipeline Itinerary
In the example provided:
// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,
If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is ready?
Thanks again,
Hal
On Fri, 2011-10-07 at 00:44 +0400, Anton Korobeynikov wrote:
> Hal...
2011 Oct 06
2
[LLVMdev] Multiple-Pipeline Itinerary
Anton,
Thanks!
What is the difference between Reserved and Required?
-Hal
On Fri, 2011-10-07 at 00:11 +0400, Anton Korobeynikov wrote:
> Hello Hal.
>
> > Is there a way to express a multiple pipeline itinerary using the
> > current scheme
> Yes, surely
>
> > (maybe some trick with setting NextCycles = 0)?
> Yep!
>
> > Specifically, consider a case
2011 Oct 06
0
[LLVMdev] Multiple-Pipeline Itinerary
Hal,
> What is the difference between Reserved and Required?
Think about them like read/write locks.
E.g. if FU is Reserved (=read lock) is can be Reserved multiple times,
but never Required.
If FU is Required (=write lock) it cannot be neither Reserved nor Required.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University