Displaying 1 result from an estimated 1 matches for "a966d1a7".
2014 Jan 28
2
[LLVMdev] ldmxcsr reordering issue
Hi,
I met troubles with jitting x86 codes when using Intrinsic::x86_sse_ldmxcsr.
The target code must execute some SSE2 instruction with DAZ/FTZ modes enabled and others with DAZ/FTZ disabled.
I'm trying to get this by emitting LDMXCSR instructions with proper flag words.
It appeared however that execution engine sometimes reorders these instructions with computational ones (say with