search for: a8r8g8b8

...ect texture format (and does not support repeat on that). Then there are some minor changes in TX_FORMAT RT_FORMAT and TEX_FILTER usage. And NVAccelInitNVx0TCL look complete different. Tested with: ./rendercheck -t fill,dcoords,scoords,mcoords,tscoords,tmcoords,triangles,bug7366 ./rendercheck -f a8r8g8b8,x8r8g8b8,r5g6b5,a8,a8b8g8r8,x8b8g8r8,x1r5g5b5 -o Clear,Src,Dst,Over,OverReverse,In,InReverse,Out,OutReverse,Atop -t blend (restricted blend test to supported formats and operation. exluded composite,cacomposite,gradients,repeat tests which seem to take forever) Signed-o...

First some data errors I get with both nv20 exa and nv20 dri/mesa. 1. RT_FORMAT LINEAR + X8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000105 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000105 LINEAR + A8R8G8B8 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x01000100:0x00000108 Ch 1/5 Class 0x0597 Mthd 0x0208 Data 0x00800080:0x00000108 The only value I found in renouveau dump was 0x00000128. Let's look at renouveau.xml nv20 <reg32 offset="0x0208" name="RT_FORMAT" type="bitfi...

Aaron Plattner (1): Skip shmblend if SHM pixmaps aren't supported Adam Jackson (4): triangles: Fix tests for conjoint and disjoint ops Be valgrind-clean Don't fail to find the a8r8g8b8 format pointlessly Enable a few more formats Alan Coopersmith (3): Update bug tracker URL in man page gitlab CI: add a basic build test t_repeat.c, t_triangles.c: convert from ISO-8859-1 to UTF-8 Emil Velikov (1): autogen.sh: use quoted string variables Eric Anholt...

...APH_ERROR - Ch 2/4 Class 0x309e Mthd 0x0300 Data > 0x00000000:0x0000000a [drm] PGRAPH_ERROR - nSource: DATA_ERROR, > nStatus: BAD_ARGUMENT [drm] PGRAPH_ERROR - Ch 2/5 Class 0x3089 > Mthd 0x0400 Data 0x00000000:0x00010001 > > 0x300 is for the texture format(A8R8G8B8) and 0x400 is for the > size (1x1). For some reason the hw doesn't like 1x1 swizzled > textures? Yeah I know what this is about. Swizzling is broken for mip maps. The first few levels swizzle fine, but after that something screws up. I think the swizzler has some limitatio...

13:28 < pmdata> ymanton> We have a bit more work to do for 8 bits texture. 13:28 < pmdata> Swizzling works by halving dimensions, and using a8r8g8b8 as format as seen in dumps for test_texture_format. 13:28 < pmdata> I nearly got text in progs/demos/texenv: http://people.freedesktop.org/~pmandin/20091011.png 13:28 < pmdata> My current patch: http://people.freedesktop.org/~pmandin/8bit_...

Currently surface_fill sets alpha incorrectly to 1.0 when drawing to A8R8G8B8 instead of the correct value. xf86-video-nouveau has the following comment confirming the issue: /* When SURFACE_FORMAT_A8R8G8B8 is used with GDI_RECTANGLE_TEXT, the * alpha channel gets forced to 0xFF for some reason. We're using * SURFACE_FORMAT_Y32 as a workaround...

...Virtual=2147287039 !!!ERROR 18:23:10/0!!!NET: 0x80040111 Couldn't create the DirectPlay8Peer Registry path = 'SOFTWARE\SigmaTeam\AlienShooter' Direct3D HAL Enum display modes 800x600 X8R8G8B8 D16 Enum display modes 1024x768 X8R8G8B8 D16 WM_PAINT Selected display mode 1024x768 A8R8G8B8 desktop X8R8G8B8 zbuffer D24S8 !!!ERROR 18:23:11/0!!!GRAPH: 0x88760B59 Couldn't create the Effect !!!ERROR 18:23:11/0!!!GRAPH: 0x88760B59 Couldn't create the Effect Any ideas.Thanks.Oh.Wine is version 9.58

...width; - float height; - } unit[2]; -} nv10_exa_state_t; -static nv10_exa_state_t state; +/* Texture/Render target formats. */ +static struct pict_format { + int exa; + int hw; +} nv10_tex_format_pot[] = { + { PICT_a8, 0x80 }, + { PICT_r5g6b5, 0x280 }, + { PICT_x8r8g8b8, 0x300 }, + { PICT_a8r8g8b8, 0x300 }, + {}, + +}, nv10_tex_format_rect[] = { + { PICT_a8, 0x980 }, + { PICT_r5g6b5, 0x880 }, + { PICT_x8r8g8b8, 0x900 }, + { PICT_a8r8g8b8, 0x900 }, + {}, + +}, nv20_tex_format_rect[] = { + { PICT_a8, 0xd80 }, + { PICT_r5g6b5, 0x880 }, + { PICT_x8r8g8b8, 0x900 }, + { PICT_a8r8g8b8, 0...

v4: Updated the wait dependancy bars based on tex component masks. This patch adds proper delays to maxwell exa shaders. Tested with rendercheck -f a8r8g8b8. I am still wondering whether the rd's are required. We could still wait on the write bars instead. eg. see "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp Trello: https://trello.com/c/6LPB2EIS/174-update-maxwell-shaders-with-proper-delays Signed-off...

...ort format name aliases test/utils: add operator aliases for lowlevel-blt-bench test/utils: add format aliases used by lowlevel-blt-bench lowlevel-blt-bench: add test name parser and self-test lowlevel-blt-bench: use the test pattern parser lowlevel-blt-bench: use a8r8g8b8 for CA solid masks lowlevel-blt-bench: move usage to a function lowlevel-blt-bench: move explanation printing lowlevel-blt-bench: make test_entry::testname const lowlevel-blt-bench: print single pattern details lowlevel-blt-bench: move speed and scaling printing...

...ort format name aliases test/utils: add operator aliases for lowlevel-blt-bench test/utils: add format aliases used by lowlevel-blt-bench lowlevel-blt-bench: add test name parser and self-test lowlevel-blt-bench: use the test pattern parser lowlevel-blt-bench: use a8r8g8b8 for CA solid masks lowlevel-blt-bench: move usage to a function lowlevel-blt-bench: move explanation printing lowlevel-blt-bench: make test_entry::testname const lowlevel-blt-bench: print single pattern details lowlevel-blt-bench: move speed and scaling printing...

...aman > On Tue, Jun 27, 2017 at 11:16 AM, Aaryaman Vasishta > <jem456.vasishta at gmail.com> wrote: > > v4: Updated the wait dependancy bars based on tex component masks. > > > > This patch adds proper delays to maxwell exa shaders. Tested with > > rendercheck -f a8r8g8b8. > > > > I am still wondering whether the rd's are required. We could > > still wait on the write bars instead. eg. see > > "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in > exacmnv110.fp > > > > Trello: > > https://trello...

https://bugs.freedesktop.org/show_bug.cgi?id=28152 Summary: corruption in FVWM window decorations Product: xorg Version: git Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org ReportedBy:

...(st 0x0) (st 0x0) >> +sched (st 0x1 wt 0x3f) (st 0x1) (st 0x1) >> fmul ftz $r3 $r3 $r7 >> > > Why are you waiting all barriers? Only $r3 is needed here. After adding a read-dep-bar and waiting on that over here, I wasn't able to pass the same number of `rendercheck -f a8r8g8b8` tests as before this patch. After a little trial and error I discovered that wt 0xc fixes it, which means that bar 3 and 4 were being used in this fmul somehow (assuming bars start from 1), which is odd because this fmul only uses $r3 and $r7, and I think it should wait on the read-dep-bar set on...

...orrectly now? Did you also remove the spurious wait dep bars between v3 and v4? On 06/27/2017 05:16 PM, Aaryaman Vasishta wrote: > v4: Updated the wait dependancy bars based on tex component masks. > > This patch adds proper delays to maxwell exa shaders. Tested with > rendercheck -f a8r8g8b8. > > I am still wondering whether the rd's are required. We could > still wait on the write bars instead. eg. see > "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp > > Trello: > https://trello.com/c/6LPB2EIS/174-update-maxwell-sha...

...lob doesn't use them (anymore) On Tue, Jun 27, 2017 at 11:16 AM, Aaryaman Vasishta <jem456.vasishta at gmail.com> wrote: > v4: Updated the wait dependancy bars based on tex component masks. > > This patch adds proper delays to maxwell exa shaders. Tested with > rendercheck -f a8r8g8b8. > > I am still wondering whether the rd's are required. We could > still wait on the write bars instead. eg. see > "sched (st 0xf wr 0x1 wt 0x2) (st 0xf wr 0x1 wt 0x2) (st 0xf)" in exacmnv110.fp > > Trello: > https://trello.com/c/6LPB2EIS/174-update-maxwell-shade...

...3f) (st 0x1) (st 0x1) >> fmul ftz $r3 $r3 $r7 >> >> >> Why are you waiting all barriers? Only $r3 is needed here. >> >> After adding a read-dep-bar and waiting on that over here, I wasn't able >> to pass the same number of `rendercheck -f a8r8g8b8` tests as before this >> patch. After a little trial and error I discovered that wt 0xc fixes it, >> which means that bar 3 and 4 were being used in this fmul somehow (assuming >> bars start from 1), which is odd because this fmul only uses $r3 and $r7, >> and I think it sh...

...+sched (st 0x1 wt 0x3f) (st 0x1) (st 0x1) > fmul ftz $r3 $r3 $r7 > > > Why are you waiting all barriers? Only $r3 is needed here. > > After adding a read-dep-bar and waiting on that over here, I wasn't able > to pass the same number of `rendercheck -f a8r8g8b8` tests as before > this patch. After a little trial and error I discovered that wt 0xc > fixes it, which means that bar 3 and 4 were being used in this fmul > somehow (assuming bars start from 1), which is odd because this fmul > only uses $r3 and $r7, and I think it should wait on...

rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to work. Very lightly tested. Instead of sticking coordinates into pushbufs, the vertex shader is modified to read them from a constbuf, indexed by vertex id. This approach could be used for all nvc0 generations, but I didn't want to rock the boat....

rendercheck -f a8r8g8b8 passes as much as on a GK208, and xv appears to work. Very lightly tested. Instead of sticking coordinates into pushbufs, the vertex shader is modified to read them from a constbuf, indexed by vertex id. This approach could be used for all nvc0 generations, but I didn't want to rock the boat....