search for: a8_pipe1

...instructions Source1 Source2 Result1 Rn:E2 Rm:E2 Rd:E2 That means Rn and Rm are read at the begin of E2 stage, Rd is produced at the end of E2, and there is 1 cycle latency. And that was implemented in llvm as such InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, Is that mean, OperandCycles and getOperandLatency were simply designed in such a way, so it is easier to use the table from cortex-a8 RTM? So OperandCycles are not actually referred to "cycle", for input operand it means at the begin of what stage and for output o...

...such as: InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>, However, I see that there is another field which I haven't specified where operand latencies are specified. Here's an example from ARMScheduleA8.td: InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, Now I'm wondering if Instead of what I had above, I should instead have specified: InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>],[150,1,1]>, ? but is that first '150' parameter there redundant? Since it's specified in the operand latency...

...tage<150, [AGU]>]>, >> >> However, I see that there is another field which I haven't specified >> where operand latencies are specified. Here's an example from >> ARMScheduleA8.td: >> >> InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, >> >> Now I'm wondering if Instead of what I had above, I should instead have >> specified: >> >> InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>],[150,1,1]>, >> >> ? >> >> but is that first '150'...