Displaying 1 result from an estimated 1 matches for "a77c1e40".
Did you mean:
a74c8e40
2015 May 21
2
[LLVMdev] Problems with instruction scheduling
Hi,
I'm trying to fix PR23405 <https://llvm.org/bugs/show_bug.cgi?id=23405> -
assert failure during instruction scheduling in llc. I have related but
more generic questions.
Is there any higher level description of the algorithm used for instruction
scheduling in this case? It is new area for me and I would love to see
bigger picture.
My currently smallest test case contains 90 DAG