Displaying 20 results from an estimated 96 matches for "a53".
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2017 May 31
6
[RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
Motivation
At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified.
When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified.
This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is "blended" for all the cores implementing the requested architecture. One example of a user being s...
2017 Jun 01
3
[RFC] Making -mcpu=generic the default for ARM armv7a and arm8a rather than -mcpu=cortex-a8 or -mcpu=cortex-a53
...2017 at 5:57 AM, Kristof Beyls <Kristof.Beyls at arm.com<mailto:Kristof.Beyls at arm.com>> wrote:
Motivation
At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified.
When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified.
This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is "blended" for all the cores implementing the requested architecture. One example of a user being s...
2017 Sep 16
3
LLVM mtriple for aarch64-win32-msvc ?
...generating the code using LLVM (writing llvm::Triple
myself and llvm::TargetRegistry::lookupTarget is working), and that's how
my bitcode is generated then using LLC to cross-compile that.
So using armv7-win32-msvc is getting me a bit closer, but what CPU,
raspberry pi 3 is running a Cortext-A53, but when I specify that in -mcpu
argument I get this error:
> llc.exe test.bc -o test.obj -filetype=obj -O3 -mtriple=armv7-win32-msvc
-mcpu=cortex-a53 -relocation-model=pic
> llc.exe failed: LLVM ERROR: CPU: 'cortex-a53' does not support ARM mode
execution!
On Fri, Sep 15, 2017 at...
2017 Jan 24
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
...ineer
Compilation Tools
ARM
From: Sanjay Patel [mailto:spatel at rotateright.com]
Sent: Tuesday, January 24, 2017 4:55 PM
To: Mehdi Amini
Cc: Evgeny Astigeevich; llvm-dev; nd
Subject: Re: [llvm-dev] [InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
On Tue, Jan 24, 2017 at 9:24 AM, Mehdi Amini <mehdi.amini at apple.com<mailto:mehdi.amini at apple.com>> wrote:
On Jan 24, 2017, at 7:18 AM, Sanjay Patel <spatel at rotateright.com<mailto:spatel at rotateright.com>> wrote:
On Mon, Jan 23, 2017...
2017 Sep 15
3
LLVM mtriple for aarch64-win32-msvc ?
Is there a way to use LLC to cross-compile some code to run on Windows IOT
on Raspberry Pi ?
I was able to convince LLVM to spit out some bitcode for this, but when I
try llc it dumps:
llc.exe test.bc -o test.obj -filetype=obj -O3 -mtriple=aarch64-win32-msvc
-mcpu=cortex-a53
Wrote crash dump file
"C:\Users\clovett\AppData\Local\Temp\llc.exe-4990d8.dmp"
0x0000000000000000 (0x0000000000000000 0x000001AE351C38E9
0x0000000000000007 0x000001AE351C38F1) <unknown module>
0x00007FF79681B7F5 (0x000001AE3526BFE0 0x000001AE35216D40
0x000001AE3526BFE0 0x00000004773...
2017 Jan 24
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
...t;
>
> Nope - this is just about perf, not correctness. Of course, the intent was that this transform should only improve perf, so I wonder if we can pin any other perf changes from this commit.
>
> I'm new to using the LNT site, but this should be the full set of results for the A53 machine in question with a baseline (r292491) before this patch and current (r292522) :
> http://llvm.org/perf/db_default/v4/nts/107364 <http://llvm.org/perf/db_default/v4/nts/107364>
>
> If these are reliable results, we have 2 perf wins (puzzle, gramschmidt) on the A53 machine. Ho...
2014 Mar 31
4
[LLVMdev] Contributing the Apple ARM64 compiler backend
...onal regressions. These are fairly easy to detect - we have a
bunch of test suites and codegen faults are easy to spot (incorrect
results). I've spent the day looking at the MC Hammer failures, and there
aren't many very bad ones. Certainly none that are horrendous to fix.
2. Performance on A53. But isn't it really just the scheduling model
that needs updating? There are no A53-specific optimizations in
Target/AArch64 that I know of.
Cheers,
James
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Brad...
2017 Jan 24
2
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
...mailto:spatel at rotateright.com <mailto:spatel at rotateright.com>]
> Sent: Sunday, January 22, 2017 10:45 PM
>
>
> To: Evgeny Astigeevich
> Cc: llvm-dev; nd
> Subject: Re: [InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
>
>
>
> I tried an experiment to remove the integer min/max bailouts from InstCombine, and it doesn't appear to change the IR in the attachment, so I doubt there's going to be any improvement.
>
> If I haven't messed up this example, this i...
2017 Jan 22
2
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
...the hack and re-run the benchmark tomorrow.
-Evgeny
From: Sanjay Patel [mailto:spatel at rotateright.com]
Sent: Sunday, January 22, 2017 8:00 PM
To: Evgeny Astigeevich
Cc: llvm-dev; nd
Subject: Re: [InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
> Do you mean to remove the hack in InstCombiner::visitICmpInst()?
Yes. Although (this just came up in D28625 too) we might need to remove multiple versions of that in order to unlock optimization:
https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombi...
2009 Jul 10
3
strange strsplit gsub problem 0 is this a bug or a string length limitation?
...?
I'd very much appreciate any suggestions
============Input script:
backtestFormula<-SPX~A1+A2+A3+A4+A5+A6+A7+A8+A9+A10+A11+A12+A13+A14+A15+A16+A17+A18+A19+A20+A21+A22+A23+A24+A25+A26+A27+A28+A29+A30+A31+A32+A33+A34+A35+A36+A37+A38+A39+A40+A41+A42+A43+A44+A45+A46+A47+A48+A49+A50+A51+A52+A53+A54+A55+A56+A57+A58+A59+A60+A61+A62+A63+A64+A65+A66+A67+A68+A69+A70+A71+A72+A73+A74+A75+A76+A77+A78+A79+A80+A81+A82+A83+A84+A85+A86+A87+A88+A89+A90+A91+A92+A93+A94+A95+A96+A97+A98+A99+A100+A101+A102+A103+A104+A105+A106+A107+A108+A109+A110+A111+A112+A113
benchmarkName = as.character(backtestFormula)...
2017 Jan 23
2
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
...evich
Senior Compiler Engineer
Compilation Tools
ARM
From: Sanjay Patel [mailto:spatel at rotateright.com]
Sent: Sunday, January 22, 2017 10:45 PM
To: Evgeny Astigeevich
Cc: llvm-dev; nd
Subject: Re: [InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
I tried an experiment to remove the integer min/max bailouts from InstCombine, and it doesn't appear to change the IR in the attachment, so I doubt there's going to be any improvement.
If I haven't messed up this example, this is amazing:
https://godbolt.org/g/...
2017 Jan 22
2
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
Hi Sanjay,
The benchmark source file: http://www.llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Shootout/sieve.c?view=markup
Clang options used to produce the initial IR: clang -DNDEBUG -O3 -DNDEBUG -mcpu=cortex-a53 -fomit-frame-pointer -O3 -DNDEBUG -w -Werror=date-time -c sieve.c -S -emit-llvm -mllvm -disable-llvm-optzns --target=aarch64-arm-linux
Opt options: opt -O3 -o /dev/null -print-before-all -print-after-all sieve.ll >& sieve.log
I used the IR (in attached sieve.zip) created with the r292487...
2014 Apr 08
2
[LLVMdev] Proposal: AArch64/ARM64 merge from EuroLLVM
Hi folks,
As Tim pointed out, we recently had the opportunity to collect 64-bit benchmark performance data for GCC 4.9, AArch64 and ARM64 compilers on a real hardware. It is a cortex-a53 device. Due to proprietary reasons we cannot share the full hardware configuration.
The preliminary results were shared at the hackers lab at EuroLLVM yesterday. For those who could not make it, below is the summarized performance data.
A positive number means the ARM64 run is better by the...
2017 Jan 20
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
Hi,
We found that today's 17.30%/11.37% performance regressions in LNT SingleSource/Benchmarks/Shootout/sieve on LNT-AArch64-A53-O3__clang_DEV__aarch64 and LNT-Thumb2v7-A15-O3__clang_DEV__thumbv7 (http://llvm.org/perf/db_default/v4/nts/daily_report/2017/1/20?filter-machine-regex=aarch64%7Carm%7Cthumb%7Cgreen) are caused by changes [rL292492] in InstCombine:
https://reviews.llvm.org/D28406 "[InstCombine] icmp sgt (shl n...
2017 Jan 24
3
[InstCombine] rL292492 affected LoopVectorizer and caused 17.30%/11.37% perf regressions on Cortex-A53/Cortex-A15 LNT machines
On Tue, Jan 24, 2017 at 1:20 PM, Sanjay Patel via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
>
> I started looking at the log files that you attached, and I'm confused.
> The code that is supposedly causing the perf regression is created by the
> loop vectorizer, right? Except the bad code is not in the "vector.body", so
> is there something peculiar about
2018 Mar 16
2
[RFC] Stop giving a default CPU to the LTO plugin?
...generate code
> for a newer target. This is generally done using the "target" function
> attribute. If this doesn't work correctly, we should fix it. It looks like
> it's currently broken; testcase:
>
> void g();
> __attribute__((target("thumb,arch=cortex-a53")))
> void f() { g(); }
>
Hmmm, allowing that makes life much more complicated. For example I
can also write:
void g();
__attribute__((target("thumb,arch=cortex-m0")))
void f() { g(); }
void i();
__attribute__((target("arm,arch=cortex-a53")))
void h() { i(); }
With...
2018 Mar 16
0
[RFC] Stop giving a default CPU to the LTO plugin?
...or a newer target. This is generally done using the "target" function
>> attribute. If this doesn't work correctly, we should fix it. It looks like
>> it's currently broken; testcase:
>>
>> void g();
>> __attribute__((target("thumb,arch=cortex-a53")))
>> void f() { g(); }
>>
>
> Hmmm, allowing that makes life much more complicated. For example I
> can also write:
> void g();
> __attribute__((target("thumb,arch=cortex-m0")))
> void f() { g(); }
>
> void i();
> __attribute__((target("a...
2014 Apr 23
2
[LLVMdev] Proposal: AArch64/ARM64 merge from EuroLLVM
...hmark?
Thanks
Gerolf
On Apr 8, 2014, at 1:33 AM, Ana Pazos <apazos at codeaurora.org> wrote:
Hi folks,
As Tim pointed out, we recently had the opportunity to collect 64-bit
benchmark performance data for GCC 4.9, AArch64 and ARM64 compilers on a
real hardware. It is a cortex-a53 device. Due to proprietary reasons we
cannot share the full hardware configuration.
The preliminary results were shared at the hackers lab at EuroLLVM
yesterday. For those who could not make it, below is the summarized
performance data.
A positive number means the ARM64 run is better by the...
2015 May 15
6
[LLVMdev] Proposal: change LNT’s regression detection algorithm and how it is used to reduce false positives
tl;dr in low data situations we don’t look at past information, and that increases the false positive regression rate. We should look at the possibly incorrect recent past runs to fix that.
Motivation: LNT’s current regression detection system has false positive rate that is too high to make it useful. With test suites as large as the llvm “test-suite” a single report will show hundreds of
2014 Jun 26
2
[LLVMdev] Contributing the Apple ARM64 compiler backend
...status we had only done our initial analysis.
> This was done without real hardware and attempted to identify poor code
> sequences but we were unable to quantify how much effect this would
> actually
> have.
>
> Since then we've done more analysis using Cortex-A57 and Cortex-A53 on an
> internal development platform.
>
> For SPEC, we are between 10% and 0% behind GCC on 9 benchmarks, and 25%
> ahead on one benchmark. Most benchmarks are less than 5% behind GCC.
>
> Because of the licencing of SPEC, I have to be quite restricted in what I
> say and I ca...