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2016 Mar 17
2
generate vectorized code
...ant<0> [ID=5] What am I missing? Any help is appreciated. > -- > Mehdi > -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160316/a374d00e/attachment.html>
2016 Mar 16
2
generate vectorized code
My question is: How do I make clang to generate assembly with vector instruction for my target? The back story is: I've added a few vector instructions to my target and confirmed that they are used by running my code on the test below and using a following command: opt i.esencia.ll -S -march=esencia -mcpu=esencia -loop-vectorize | llc -mcpu=esencia -o i.esencia.s target datalayout =