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...mvn q8, q10 vsub.i8 q11, q3, q14 vsub.i8 q12, q15, q14 vsub.i8 q13, q8, q14 vst3.8 {d22, d24, d26}, [r8]! vst3.8 {d23, d25, d27}, [r8] cheers, --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131014/a05ed9f0/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: test.c Type: text/x-csrc Size: 398 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131014/a05ed9f0/attachment.c>

Renato, can you post the c code for the function and the assembly that gcc produces? Your initial example could be well handled by vectorization of strided loops (and the mentioning of VLD3(.8?)/VST3(.8?) lead me to assume that this is what happened). But the LLVM-IR you sent has a store of 0 in there ;) and strides by 4. Thanks, Arnold Vectorization of strided loops: I am using float as the

This is almost ideal for SLP vectorization, except for two problems: 1. We have 4 stores to consecutive locations, but the last element is the constant zero, and not an additional SUB. At the moment we don’t have support for idempotence operations, but this is something that we should add. 2. The values that we are subtracting come from 3 loads. We usually load 4 elements from memory, or