Displaying 2 results from an estimated 2 matches for "a0557183".
2013 Mar 23
0
[LLVMdev] Simpler types in TableGen isel patterns
...e errors.
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How come the Hexagone backend is able to get away with that then?
def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,
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2013 Mar 21
9
[LLVMdev] Simpler types in TableGen isel patterns
Currently, instruction selection patterns are defined like this:
def : Pat<(and (not GR32:$src1), GR32:$src2),
(ANDN32rr GR32:$src1, GR32:$src2)>;
def : Pat<(and (not GR64:$src1), GR64:$src2),
(ANDN64rr GR64:$src1, GR64:$src2)>;
TableGen infers the types of $src1 and $src2 from the specified register classes, and that is the only purpose of the register