Displaying 1 result from an estimated 1 matches for "_z9test_mathv".
2019 Jan 22
2
Different SelectionDAGs for same CPU
Hi,
I used 2 different compilers to compile the same IR for the same custom target.
The LLVM IR code is
define i32 @_Z9test_mathv() #0 {
%a = alloca i32, align 4
%1 = load i32, i32* %a, align 4
ret i32 %1
}
Before instruction selection, the Selection DAGs are the same:
Optimized legalized selection DAG: %bb.0 '_Z9test_mathv:'
SelectionDAG has 7 nodes:
t0: ch = EntryToken
t4: i32,ch = load<(dereference...