Displaying 3 results from an estimated 3 matches for "_z5__anyi_param_0".
2012 Jul 10
2
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...march=nvptx64 test.ll -o test.ptx
> cat test.ptx
//
// Generated by LLVM NVPTX Back-End
//
.version 3.0
.target sm_10, texmode_independent
.address_size 64
// .globl _Z5__anyi
.visible .global .align 4 .b8 __local_depot0[8];
.func (.reg .b32 func_retval0) _Z5__anyi(
.reg .b32 _Z5__anyi_param_0
) // @_Z5__anyi
{
.reg .b64 %SP;
.reg .b64 %SPL;
.reg .pred %p<396>;
.reg .s16 %rc<396>;
.reg .s16 %rs<396>;
.reg .s32 %r<396>;
.reg .s64 %rl<396>;
.reg .f32 %f<396>;
.reg .f64 %fl&...
2012 Jul 10
0
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
...nerated by LLVM NVPTX Back-End
> //
>
> .version 3.0
> .target sm_10, texmode_independent
> .address_size 64
>
>
> // .globl _Z5__anyi
> .visible .global .align 4 .b8 __local_depot0[8];
>
> .func (.reg .b32 func_retval0) _Z5__anyi(
> .reg .b32 _Z5__anyi_param_0
> ) // @_Z5__anyi
> {
> .reg .b64 %SP;
> .reg .b64 %SPL;
> .reg .pred %p<396>;
> .reg .s16 %rc<396>;
> .reg .s16 %rs<396>;
> .reg .s32 %r<396>;
> .reg .s64 %rl<396>;
&g...
2012 Jul 10
1
[LLVMdev] [NVPTX] CUDA inline PTX asm definitions scoping "{" "}" is broken
.../ Generated by LLVM NVPTX Back-End
> //
>
> .version 3.0
> .target sm_10, texmode_independent
> .address_size 64
>
>
> // .globl _Z5__anyi
> .visible .global .align 4 .b8 __local_depot0[8];
>
> .func (.reg .b32 func_retval0) _Z5__anyi(
> .reg .b32 _Z5__anyi_param_0
> ) // @_Z5__anyi
> {
> .reg .b64 %SP;
> .reg .b64 %SPL;
> .reg .pred %p<396>;
> .reg .s16 %rc<396>;
> .reg .s16 %rs<396>;
> .reg .s32 %r<396>;
> .reg .s64 %rl<396>;
&g...