search for: _xyzw

...RITEMASK_Z) +#define _XYW(v) ureg_writemask((v), TGSI_WRITEMASK_X | TGSI_WRITEMASK_Y | TGSI_WRITEMASK_W) +#define _XZW(v) ureg_writemask((v), TGSI_WRITEMASK_Y | TGSI_WRITEMASK_Z | TGSI_WRITEMASK_W) +#define _YZW(v) ureg_writemask((v), TGSI_WRITEMASK_Y | TGSI_WRITEMASK_Z | TGSI_WRITEMASK_W) +#define _XYZW(v) ureg_writemask((v), TGSI_WRITEMASK_X | TGSI_WRITEMASK_Y | TGSI_WRITEMASK_Z | TGSI_WRITEMASK_W) + +#define _SAT(v) ureg_saturate(v) +#define _PRED(v, n, x, y, z, w) ureg_predicate(v, n, x, y, z, w) +#define _IND(r, a) ureg_dst_indirect(r, _src(a)) +#define _UNDEF ureg_dst_undef() +#define _IS_UND...

Hi Tom, Thanks a lot for your explanations, now it makes a lot more sense ;) I had a slightly closer look at the R600 packetizer, and the issue is that the third LSHL instruction has both an implicit use and *afterwards* an implicit def of T1_XYZW. The latter def causes the current ScheduleDAGInstrs implementation to ignore the implicit use, thus the ScheduleDAG only contains an anti-dependency from the second to the third LSHL and the packetizer can bundle the instructions. If the order of the implicit-defs and implicit-use would be dif...

...ruction bundles" pass: %T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0 %T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def> %T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def> Hence, my patch affects either the R600 Packetizer or the R600 Control Flow Finalizer pa...