Displaying 5 results from an estimated 5 matches for "_p_vec_full".
2013 Mar 01
2
[LLVMdev] Interesting post increment situation in DAG combiner
...s66 = phi i32 [ 0, %p.loop_body.lr.ph.us78 ], [
%p.next_loopiv.us67, %p.loop_body.us65 ]
%vector_ptr.us70 = bitcast i16* %p_arrayidx.us69.phi to <4 x i16>*
%p.next_loopiv.us67 = add nsw i32 %p.loopiv48.us66, 4 <<<<<<<<<<<<<<<<<<
IV
%_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
<<<<<<<<<<<<<<<<<<<Load
%add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr.us70, align 16
<<<<...
2013 Mar 01
0
[LLVMdev] Interesting post increment situation in DAG combiner
...lr.ph.us78 ], [
> %p.next_loopiv.us67, %p.loop_body.us65 ]
> %vector_ptr.us70 = bitcast i16* %p_arrayidx.us69.phi to <4 x i16>*
> %p.next_loopiv.us67 = add nsw i32 %p.loopiv48.us66, 4
> <<<<<<<<<<<<<<<<<<
> IV
> %_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
> <<<<<<<<<<<<<<<<<<<Load
> %add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
> store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr.us70, align
>...
2013 Mar 01
1
[LLVMdev] Interesting post increment situation in DAG combiner
...ext_loopiv.us67, %p.loop_body.us65 ]
> > %vector_ptr.us70 = bitcast i16* %p_arrayidx.us69.phi to <4 x i16>*
> > %p.next_loopiv.us67 = add nsw i32 %p.loopiv48.us66, 4
> > <<<<<<<<<<<<<<<<<<
> > IV
> > %_p_vec_full.us71 = load <4 x i16>* %vector_ptr.us70, align 16
> > <<<<<<<<<<<<<<<<<<<Load
> > %add5p_vec.us72 = add <4 x i16> %_p_vec_full.us71, %5
> > store <4 x i16> %add5p_vec.us72, <4 x i16>* %vector_ptr....
2013 Mar 01
0
[LLVMdev] parallel loop metadata simplification
----- Original Message -----
> From: "Paul Redmond" <paul.redmond at intel.com>
> To: "llvmdev at cs.uiuc.edu Dev" <llvmdev at cs.uiuc.edu>
> Sent: Thursday, February 28, 2013 1:30:57 PM
> Subject: [LLVMdev] parallel loop metadata simplification
>
> Hi,
>
> I've been working on clang codegen for #pragma ivdep and creating the
>
2013 Feb 28
5
[LLVMdev] parallel loop metadata simplification
Hi,
I've been working on clang codegen for #pragma ivdep and creating the llvm.mem.parallel_loop_access metadata seems quite difficult. The main problem is that there are so many places where loads and stores are created and all of them need to be changed when emitting a parallel loop. Note that creating llvm.loop.parallel is not a problem.
One option is to modify IRBuilder to enable