search for: _nouveau_clock_init

https://bugs.freedesktop.org/show_bug.cgi?id=72181 Priority: medium Bug ID: 72181 Assignee: nouveau at lists.freedesktop.org Summary: [v3.13][regression] NULL pointer deref (_nouveau_clock_init) QA Contact: xorg-team at lists.x.org Severity: normal Classification: Unclassified OS: All Reporter: ronald645 at gmail.com Hardware: Other Status: NEW Version: git Component: Driver/nouveau Produc...

...ntly won't build against -next because it uses drm_sysfs_connector_add/remove which are not available anymore (replaced by drm_connector_register/unregister I believe). Oh and while I'm at it, there seems to be a typo in line 131 of clock.h, which should read _nouveau_clock_fini and not _nouveau_clock_init. >> >> The last patch adds the GK20A clock device. Arguably the clock can be seen as a >> stripped-down version of what is seen on NVE0, however instead of using NVE0 >> support has been written from scratch using the ChromeOS kernel as a basis. >> There are several r...

...proper fix here. -ilia diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c index ce82dc4..acc4ac8 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c @@ -411,6 +411,7 @@ _nouveau_clock_init(struct nouveau_object *object) memset(&clk->bstate, 0x00, sizeof(clk->bstate)); INIT_LIST_HEAD(&clk->bstate.list); clk->bstate.pstate = 0xff; + if (!clock) return 0; while (clock->name != nv_clk_src_max) { ret = clk->r...

...3,7 @@ struct nouveau_clocks { int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *, struct nouveau_oclass *, - struct nouveau_clocks *, int, void **); + struct nouveau_clocks *, bool, int, void **); void _nouveau_clock_dtor(struct nouveau_object *); int _nouveau_clock_init(struct nouveau_object *); #define _nouveau_clock_fini _nouveau_subdev_fini diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c index dd62bae..80ad9d3 100644 --- a/nvkm/subdev/clock/base.c +++ b/nvkm/subdev/clock/base.c @@ -346,8 +346,8 @@ nouveau_clock_ustate_update(struct nouveau_clo...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Hope I understood you correctly wrt the mem exec stuff. nvkm/subdev/fb/ramnv50.c | 2 +- nvkm/subdev/fb/ramnva3.c | 2 +- nvkm/subdev/fb/ramnvc0.c | 2 +- nvkm/subdev/fb/ramnve0.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/nvkm/subdev/fb/ramnv50.c b/nvkm/subdev/fb/ramnv50.c index ef91b6e..e5d12c2 100644

...struct nouveau_object *, > struct nouveau_oclass *, > - struct nouveau_clocks *, int, void **); > + struct nouveau_clocks *, bool, int, void **); > void _nouveau_clock_dtor(struct nouveau_object *); > int _nouveau_clock_init(struct nouveau_object *); > #define _nouveau_clock_fini _nouveau_subdev_fini > diff --git a/nvkm/subdev/clock/base.c b/nvkm/subdev/clock/base.c > index dd62bae..80ad9d3 100644 > --- a/nvkm/subdev/clock/base.c > +++ b/nvkm/subdev/clock/base.c > @@ -346,8 +346,8 @@ nouveau_clock_us...

...---------------- CPU: 0 PID: 682 Comm: modprobe Not tainted 3.13.0-rc3_exact-293199-g374b105 #379 Hardware name: / , BIOS GB85010A.86A.0063.P14.0107182015 07/18/2001 task: ef5b1a80 ti: ef5d8000 task.ti: ef5d8000 EIP: 0060:[<f0cfe995>] EFLAGS: 00010246 CPU: 0 EIP is at _nouveau_clock_init+0x59/0x102 [nouveau] EAX: c0f58240 EBX: 00000000 ECX: 00000000 EDX: 00000000 ESI: c0f58200 EDI: c0f582bc EBP: ef5d9b24 ESP: ef5d9b00 DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 0068 CR0: 8005003b CR2: 00000000 CR3: 2f5ba000 CR4: 000007d0 Stack: c0d18cc4 ef5d9b24 f0cef579 c0d18c00 00000005 c0f58238 c0...

...ff, 0, "vdec", 1000 }, + { nv_clk_src_max } +}; + +struct nouveau_oclass * +nvaa_clock_oclass = &(struct nv50_clock_oclass) { + .base.handle = NV_SUBDEV(CLOCK, 0xaa), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvaa_clock_ctor, + .dtor = _nouveau_clock_dtor, + .init = _nouveau_clock_init, + .fini = _nouveau_clock_fini, + }, + .domains = nvaa_domains, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h new file mode 100644 index 0000000..619bfbd --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h...

...ff, 0, "vdec", 1000 }, + { nv_clk_src_max } +}; + +struct nouveau_oclass * +nvaa_clock_oclass = &(struct nv50_clock_oclass) { + .base.handle = NV_SUBDEV(CLOCK, 0xaa), + .base.ofuncs = &(struct nouveau_ofuncs) { + .ctor = nvaa_clock_ctor, + .dtor = _nouveau_clock_dtor, + .init = _nouveau_clock_init, + .fini = _nouveau_clock_fini, + }, + .domains = nvaa_domains, +}.base; diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h new file mode 100644 index 0000000..ee7575f --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.h...

Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to

This series adds support for reclocking on GK20A. The first two patches touch the clock subsystem to allow GK20A to operate, by making the presence of the thermal and voltage devices optional, and allowing pstates to be provided directly instead of being probed using the BIOS (which Tegra does not have). The last patch adds the GK20A clock device. Arguably the clock can be seen as a stripped-down

Second version of the gk20a clock patches. I have tried to keep the therm and volt devices mandatory in the clock driver, but unfortunately they are too tied to bios to allow this, at least for the moment. Consequently this version is mostly a port of the first version to Ben's tree. Ben, please let me know what I have done wrong in terms of integration to your tree, as the main purpose of