search for: _mm_srai_epi32

...const* buf) { +#ifdef __SSSE3__ + return _mm_lddqu_si128(buf); // same as loadu on all but the oldest SSSE3 CPUs +#else + return _mm_loadu_si128(buf); +#endif +} + +#ifndef __SSSE3__ +static inline __m128i sse_interleave_odd_epi16(__m128i a, __m128i b) { + return _mm_packs_epi32( + _mm_srai_epi32(a, 16), + _mm_srai_epi32(b, 16) + ); +} + +static inline __m128i sse_interleave_even_epi16(__m128i a, __m128i b) { + return sse_interleave_odd_epi16( + _mm_slli_si128(a, 2), + _mm_slli_si128(b, 2) + ); +} + +static inline __m128i sse_mulu_odd_epi8(__m128i a, __m128i b)...

...dqu_si128(buf); // same as loadu on all but the > oldest SSSE3 CPUs > +#else > + return _mm_loadu_si128(buf); > +#endif > +} > + > +#ifndef __SSSE3__ > +static inline __m128i sse_interleave_odd_epi16(__m128i a, __m128i b) { > + return _mm_packs_epi32( > + _mm_srai_epi32(a, 16), > + _mm_srai_epi32(b, 16) > + ); > +} > + > +static inline __m128i sse_interleave_even_epi16(__m128i a, __m128i b) { > + return sse_interleave_odd_epi16( > + _mm_slli_si128(a, 2), > + _mm_slli_si128(b, 2) > + ); > +} > + > +s...

...static inline __m128i sse_load_si128(__m128i_u* buf) { + return _mm_lddqu_si128(buf); // same as loadu on all but the oldest SSSE3 CPUs +} + +__attribute__ ((target ("sse2"))) static inline __m128i sse_interleave_odd_epi16(__m128i a, __m128i b) { + return _mm_packs_epi32( + _mm_srai_epi32(a, 16), + _mm_srai_epi32(b, 16) + ); +} + +__attribute__ ((target ("sse2"))) static inline __m128i sse_interleave_even_epi16(__m128i a, __m128i b) { + return sse_interleave_odd_epi16( + _mm_slli_si128(a, 2), + _mm_slli_si128(b, 2) + ); +} + +__attribute__ ((t...

...but the >> oldest SSSE3 CPUs >> +#else >> + return _mm_loadu_si128(buf); >> +#endif >> +} >> + >> +#ifndef __SSSE3__ >> +static inline __m128i sse_interleave_odd_epi16(__m128i a, __m128i b) { >> + return _mm_packs_epi32( >> + _mm_srai_epi32(a, 16), >> + _mm_srai_epi32(b, 16) >> + ); >> +} >> + >> +static inline __m128i sse_interleave_even_epi16(__m128i a, __m128i b) { >> + return sse_interleave_odd_epi16( >> + _mm_slli_si128(a, 2), >> + _mm_slli_si128(b, 2) &gt...

...m128i_u* buf) { > + return _mm_lddqu_si128(buf); // same as loadu on all but the > oldest SSSE3 CPUs > +} > + > +__attribute__ ((target ("sse2"))) static inline __m128i > sse_interleave_odd_epi16(__m128i a, __m128i b) { > + return _mm_packs_epi32( > + _mm_srai_epi32(a, 16), > + _mm_srai_epi32(b, 16) > + ); > +} > + > +__attribute__ ((target ("sse2"))) static inline __m128i > sse_interleave_even_epi16(__m128i a, __m128i b) { > + return sse_interleave_odd_epi16( > + _mm_slli_si128(a, 2), > + _mm_sll...

What do you base this on? Per https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html : "For the x86-32 compiler, you must use -march=cpu-type, -msse or -msse2 switches to enable SSE extensions and make this option effective. For the x86-64 compiler, these extensions are enabled by default." That reads to me like we're fine for SSE2. As stated in my comments, SSSE3 support must be

Hi all, This is Linfeng Zhang from Google. I'll work on ARM NEON optimization in the next few months. I'm submitting 2 patches in the following couple of emails, which have the new created celt_fir_neon(). I revised celt_fir_c() to not pass in argument "mem" in Patch 1. If there are concerns to this change, please let me know. Many thanks to your comments. Linfeng Zhang

I rebased my previous 3 patches to the current master with minor changes. Patches 1 to 3 replace all my previous submitted patches. Patches 4 and 5 are new. Thanks, Linfeng Zhang