Displaying 3 results from an estimated 3 matches for "_mm_set1_ps".
2014 Oct 13
2
[LLVMdev] Unexpected spilling of vector register during lane extraction on some x86_64 targets
..._si128(x), 23),
_mm_set1_epi32(127));
const __m128 s = _mm_or_ps(
_mm_andnot_ps(_mm_castsi128_ps(_mm_set1_epi32(0xff << 23)), x),
_mm_castsi128_ps(_mm_set1_epi32(0x7f << 23)));
const __m128 exp = _mm_cvtepi32_ps(iexp);
const __m128i quot = _mm_cvttps_epi32(_mm_div_ps(exp, _mm_set1_ps(3.f)));
const __m128i rem = _mm_sub_epi32(iexp, _mm_mullo_epi16(quot,
_mm_set1_epi32(0x10003)));
const __m128 entry = _mm_setr_ps( // 'rem' gets spilled depending on
version of lane extractor used
table[geti(rem, 0)],
table[geti(rem, 1)],
table[geti(rem, 2)],
table[geti(rem, 3)]);
return...
2016 May 31
2
[PATCH 1/2] Modify autoconf tests for intrinsics to stop clang from optimizing them away.
...[
[OPUS_X86_MAY_HAVE_SSE],
[OPUS_X86_PRESUME_SSE],
[[#include <xmmintrin.h>
+ #include <time.h>
]],
[[
- static __m128 mtest;
- mtest = _mm_setzero_ps();
+ __m128 mtest;
+ mtest = _mm_set1_ps((float)time(NULL));
+ mtest = _mm_mul_ps(mtest, mtest);
+ return _mm_cvtss_si32(mtest);
]]
)
AS_IF([test x"$OPUS_X86_MAY_HAVE_SSE" = x"1" && test x"$OPUS_X86_PRESUME_SSE" != x"1"],
@@ -539,10 +543,13 @@...
2017 Jun 14
2
Default FPENV state
Hi,
We are interesting in expanding some vector operations directly in the
IR form as constants https://reviews.llvm.org/D33406,
for example: _mm256_cmp_ps("any input", "any input", _CMP_TRUE_UQ)
should produce -1, -1, -1, ... vector, but for some values for example
"1.00 -nan" if FPU exceptions were enabled this operation triggers the
exception. Here is the question: