Displaying 15 results from an estimated 15 matches for "_mm_cvtsi128_si32".
2014 Oct 13
2
[LLVMdev] Unexpected spilling of vector register during lane extraction on some x86_64 targets
...g/no-spilling code put on conditional
compile:
#if __SSE4_1__ != 0
#include <smmintrin.h>
#else
#include <emmintrin.h>
#endif
#include <stdint.h>
#include <assert.h>
#if SPILLING_ENSUES == 1
static int32_t geti(const __m128i v, const size_t i)
{
switch (i) {
case 0:
return _mm_cvtsi128_si32(v);
case 1:
return _mm_cvtsi128_si32(_mm_shuffle_epi32(v, 0xe5));
case 2:
return _mm_cvtsi128_si32(_mm_shuffle_epi32(v, 0xe6));
case 3:
return _mm_cvtsi128_si32(_mm_shuffle_epi32(v, 0xe7));
}
assert(0);
return -1;
}
#else
static int32_t geti(const __m128i v, const size_t i)
{
switch (i) {
case 0:...
2016 May 31
2
[PATCH 1/2] Modify autoconf tests for intrinsics to stop clang from optimizing them away.
...h>
+ #include <time.h>
]],
[[
- static __m128i mtest;
- mtest = _mm_setzero_si128();
+ __m128i mtest;
+ mtest = _mm_set1_epi32((int)time(NULL));
+ mtest = _mm_mul_epu32(mtest, mtest);
+ return _mm_cvtsi128_si32(mtest);
]]
)
AS_IF([test x"$OPUS_X86_MAY_HAVE_SSE2" = x"1" && test x"$OPUS_X86_PRESUME_SSE2" != x"1"],
@@ -557,11 +564,13 @@ AS_IF([test x"$enable_intrinsics" = x"yes"],[
[OPUS_X86_MAY_HAVE_SSE4_1]...
2016 May 02
1
[PATCH] workaround for a bug in MSVC 2015 U2
...at somebody else will find what's wrong and will create a bugreport...
Well, here is the link: https://connect.microsoft.com/VisualStudio/feedback/details/2659191/incorrect-code-generation-for-x86-64
It seems that MSVC miscompiles
abs_residual_partition_sums[partition] = (FLAC__uint32)_mm_cvtsi128_si32(mm_sum);
into
movq QWORD PTR [rsi], xmm2
So it incorrectly copies 8 bytes from mm_sum to abs_residual_partition_sums[partition]
(it should copy 4 lower bytes and zero out 4 upper bytes).
It should be something like
movd eax, xmm2
movq QWORD PTR [rsi], rax
2014 Jan 24
2
PATCH for lpc_intrin_sse41.c: faster shifts
It turns out that int64 shift is quite slow...
This patch changes the code from:
(FLAC__int32)(xmm.m128i_i64[0] >> lp_quantization)
into:
_mm_cvtsi128_si32(_mm_srli_epi64(xmm, lp_quantization));
Encoding of 24-bit .wav files with 32-bit FLAC became noticeably faster.
The new code works only if quantization <= 32, but its max value is 15 so the code always work.
(max_shiftlimit == (1 << (FLAC__SUBFRAME_LPC_QLP_SHIFT_LEN-1)) - 1 == 15)
2016 May 02
3
[PATCH] MSVC2015U2 workaround, version 2
Here's a new version of a patch that fixes a problem with MSVC2105 update2,
but it doesn't disable any optimization, so the resulting encoding
performance should be almost unaffected by this workaround.
MSVC compiles
abs_residual_partition_sums[partition] = (FLAC__uint32)_mm_cvtsi128_si32(mm_sum);
into this:
movq QWORD PTR [rsi], xmm2
while it should be
movd eax, xmm2
mov QWORD PTR [rsi], rax
With this patch, MSVC emits
movq QWORD PTR [rsi], xmm2
mov DWORD PTR [rsi+4], r9d
so the price of this workaround is 1 extra write instruction p...
2014 Jan 30
0
PATCH for lpc_intrin_sse41.c: faster shifts
lvqcl wrote:
> It turns out that int64 shift is quite slow...
>
> This patch changes the code from:
> (FLAC__int32)(xmm.m128i_i64[0] >> lp_quantization)
> into:
> _mm_cvtsi128_si32(_mm_srli_epi64(xmm, lp_quantization));
>
> Encoding of 24-bit .wav files with 32-bit FLAC became noticeably faster.
>
>
> The new code works only if quantization <= 32, but its max value is 15 so the code always work.
> (max_shiftlimit == (1 << (FLAC__SUBFRAME_LPC_QLP_...
2016 May 02
2
[PATCH] workaround for a bug in MSVC 2015 U2
Erik de Castro Lopo wrote:
>> As I wrote earlier, MSVC 2015 U2 incorrectly compiles
>> stream_encoder_intrin_*.c files for x86-64 platform.
>> As a result, flac works, but compression ratio is close to 1.
>> This patch disables some compiler optimizations, and
>> compression ratio reverts back to normal values.
>
> Rather than having the same chunk of code in
2015 Mar 13
1
[RFC PATCH v3] Intrinsics/RTCD related fixes. Mostly x86.
...i + 0]);
-
- inVec1_3210 = _mm_mullo_epi32(inVec1_3210, inVec2_3210);
-
- acc1 = _mm_add_epi32(acc1, inVec1_3210);
- i += 4;
- }
-
- acc1 = _mm_add_epi32(acc1, _mm_unpackhi_epi64(acc1, acc1));
- acc1 = _mm_add_epi32(acc1, _mm_shufflelo_epi16(acc1, 0x0E));
-
- sum += _mm_cvtsi128_si32(acc1);
-
- for (;i<N;i++)
- {
- sum = silk_SMLABB(sum, x[i], y[i]);
- }
+#include <xmmintrin.h>
+#include "arch.h"
- return sum;
+void xcorr_kernel_sse(const opus_val16 *x, const opus_val16 *y, opus_val32 sum[4], int len)
+{
+ int j;
+ __m128 xsum1, xsum2...
2015 Mar 12
1
[RFC PATCHv2] Intrinsics/RTCD related fixes. Mostly x86.
...i + 0]);
-
- inVec1_3210 = _mm_mullo_epi32(inVec1_3210, inVec2_3210);
-
- acc1 = _mm_add_epi32(acc1, inVec1_3210);
- i += 4;
- }
-
- acc1 = _mm_add_epi32(acc1, _mm_unpackhi_epi64(acc1, acc1));
- acc1 = _mm_add_epi32(acc1, _mm_shufflelo_epi16(acc1, 0x0E));
-
- sum += _mm_cvtsi128_si32(acc1);
-
- for (;i<N;i++)
- {
- sum = silk_SMLABB(sum, x[i], y[i]);
- }
+#include <xmmintrin.h>
+#include "arch.h"
- return sum;
+void xcorr_kernel_sse(const opus_val16 *x, const opus_val16 *y, opus_val32 sum[4], int len)
+{
+ int j;
+ __m128 xsum1, xsum2...
2015 Mar 02
13
Patch cleaning up Opus x86 intrinsics configury
The attached patch cleans up Opus's x86 intrinsics configury.
It:
* Makes ?enable-intrinsics work with clang and other non-GCC compilers
* Enables RTCD for the floating-point-mode SSE code in Celt.
* Disables use of RTCD in cases where the compiler targets an instruction set by default.
* Enables the SSE4.1 Silk optimizations that apply to the common parts of Silk when Opus is built in
2015 Mar 18
5
[RFC PATCH v1 0/4] Enable aarch64 intrinsics/Ne10
Hi All,
Since I continue to base my work on top of Jonathan's patch,
and my previous Ne10 fft/ifft/mdct_forward/backward patches,
I thought it would be better to just post all new patches
as a patch series. Please let me know if anyone disagrees
with this approach.
You can see wip branch of all latest patches at
https://git.linaro.org/people/viswanath.puttagunta/opus.git
Branch:
2015 Mar 31
6
[RFC PATCH v1 0/5] aarch64: celt_pitch_xcorr: Fixed point series
Hi Timothy,
As I mentioned earlier [1], I now fixed compile issues
with fixed point and resubmitting the patch.
I also have new patch that does intrinsics optimizations
for celt_pitch_xcorr targetting aarch64.
You can find my latest work-in-progress branch at [2]
For reference, you can use the Ne10 pre-built libraries
at [3]
Note that I am working with Phil at ARM to get my patch at [4]
2015 May 08
8
[RFC PATCH v2]: Ne10 fft fixed and previous 0/8]
Hi All,
As per Timothy's suggestion, disabling mdct_forward
for fixed point. Only effects
armv7,armv8: Extend fixed fft NE10 optimizations to mdct
Rest of patches are same as in [1]
For reference, latest wip code for opus is at [2]
Still working with NE10 team at ARM to get corner cases of
mdct_forward. Will update with another patch
when issue in NE10 gets fixed.
Regards,
Vish
[1]:
2015 May 15
11
[RFC V3 0/8] Ne10 fft fixed and previous
Hi All,
Changes from RFC v2 [1]
armv7,armv8: Extend fixed fft NE10 optimizations to mdct
- Overflow issue fixed by Phil at ARM. Ne10 wip at [2]. Should be upstream soon.
- So, re-enabled using fixed fft for mdct_forward which was disabled in RFCv2
armv7,armv8: Optimize fixed point fft using NE10 library
- Thanks to Jonathan Lennox, fixed some build fixes on iOS and some copy-paste errors
Rest
2015 Apr 28
10
[RFC PATCH v1 0/8] Ne10 fft fixed and previous
Hello Timothy / Jean-Marc / opus-dev,
This patch series is follow up on work I posted on [1].
In addition to what was posted on [1], this patch series mainly
integrates Fixed point FFT implementations in NE10 library into opus.
You can view my opus wip code at [2].
Note that while I found some issues both with the NE10 library(fixed fft)
and with Linaro toolchain (armv8 intrinsics), the work