Displaying 10 results from an estimated 10 matches for "_i32".
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...t, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...t, $src0, $src1"),
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
}
defm AND : BinaryOpMCInt<IL_OP_AND, and>;
I want to turn this into a register/immediate pattern by changing it to:
class ILFormat<dag outs, dag ins...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> clas...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
> multiclass BinaryOpMCInt<ILOpCode OpCode, SDNode OpNode> {
> def _i8 : BinaryOp<OpCode, OpNode, GPRI8, GPRI8, GPRI8>;
>
> def _i16 : BinaryOp<OpCode, OpNode, GPRI16, GPRI16, GPRI16>;
> def _i32 : BinaryOp<OpCode, OpNode, GPRI32, GPRI32, GPRI32>;
> def _i64 : BinaryOp<OpCode, OpNode, GPRI64, GPRI64, GPRI64>;
> }
> defm AND : BinaryOpMCInt<IL_OP_AND, and>;
>
> I want to turn this into a register/immediate pattern by changing it to:
> clas...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
...lticlass's that
define other classes, but with using patterns inside of a multiclass to
reduce redundant code.
For example:
multiclass IntSubtract<SDNode node>
{
def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
(ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
}
or something similar.
I just want to write the pattern once and then have it apply to multiple
register types, i.e. a generic pattern rule for many different register
classes.
Thanks...
2009 Feb 10
0
[LLVMdev] Multiclass patterns
...r classes, but with using patterns inside of a multiclass to
> reduce redundant code.
> For example:
> multiclass IntSubtract<SDNode node>
> {
> def _i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1),
> (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>;
> def _i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1),
> (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>;
> }
>
> or something similar.
> I just want to write the pattern once and then have it apply to multiple
> register types, i.e. a generic pattern rule for many differe...
2008 Oct 06
1
[LLVMdev] sign extensions on loads?
...ops node:$ptr), (ld node:$ptr), [{
return isGenericLoad(dyn_cast<LoadSDNode>(N));
}]>;
def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>;
// Load Memory Operations
multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> {
def _i32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (i32 GPR:$dst), (OpNode addr:$ptr))]>;
def _f32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr),
asm, [(set (f32 GPR:$dst), (OpNode addr:$ptr))]>;
def _i64 : OneInOneOut<IL_OP_MO...
2009 Feb 10
2
[LLVMdev] Multiclass patterns
Is there a way to define a multi-class pattern in tablegen?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
S1-609 One AMD Place
Sunnyvale, CA. 94085
P: 408-749-3966
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2009 Feb 10
0
[LLVMdev] Multiclass patterns
On Mon, Feb 9, 2009 at 5:17 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> Is there a way to define a multi-class pattern in tablegen?
>
Yes. See "multiclass" and "defm" in, say, X86Instr64bit.td, et al.
-bw
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the