search for: _gp_disp

Displaying 20 results from an estimated 21 matches for "_gp_disp".

2013 Sep 17
2
[LLVMdev] forcing two instructions to be together
...ous mechanisms that can be applied, depending on exactly what the constraints are that you need to preserve. >> >> —Owen > I have two machine instructions that I need to be together. > > BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) > .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); > BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) > .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); > > It's in Mips16ISelDagToDag.cpp > > these two have to be together because they are both part of a complex pc relative ca...
2013 Sep 17
2
[LLVMdev] forcing two instructions to be together
...at the constraints are that you > need to preserve. > >>> > >>> -Owen > >> I have two machine instructions that I need to be together. > >> > >> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) > >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); > >> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) > >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); > >> > >> It's in Mips16ISelDagToDag.cpp > >> > >> these two have to be together...
2013 Sep 17
0
[LLVMdev] forcing two instructions to be together
...be applied, depending on exactly what the constraints are that you need to preserve. >>> >>> —Owen >> I have two machine instructions that I need to be together. >> >> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); >> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) >> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); >> >> It's in Mips16ISelDagToDag.cpp >> >> these two have to be together because they are both part of...
2013 Sep 18
2
[LLVMdev] forcing two instructions to be together
...the constraints are that you >> need to preserve. >>>>> -Owen >>>> I have two machine instructions that I need to be together. >>>> >>>> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) >>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); >>>> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) >>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); >>>> >>>> It's in Mips16ISelDagToDag.cpp >>>> >>>> these two...
2013 Sep 18
0
[LLVMdev] forcing two instructions to be together
...the constraints are that you >> need to preserve. >>>>> -Owen >>>> I have two machine instructions that I need to be together. >>>> >>>> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) >>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); >>>> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) >>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); >>>> >>>> It's in Mips16ISelDagToDag.cpp >>>> >>>> these two...
2013 Sep 18
0
[LLVMdev] forcing two instructions to be together
...t you >>> need to preserve. >>>>>> -Owen >>>>> I have two machine instructions that I need to be together. >>>>> >>>>> BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmAlignX16), V0) >>>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); >>>>> BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) >>>>> .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); >>>>> >>>>> It's in Mips16ISelDagToDag.cpp >>>>> >&gt...
2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
...quot;ch8_3.bc" .text .globl _Z5sum_iiz .align 2 .type _Z5sum_iiz, at function .set nomips16 # @_Z5sum_iiz .ent _Z5sum_iiz _Z5sum_iiz: .cfi_startproc .frame $sp,64,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -64 $tmp2: .cfi_def_cfa_offset 64 sw $ra, 60($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -4 addu $gp, $2, $25 sw $7, 76($sp) sw $6, 72($sp) sw $5, 68($sp) lw $3, %got(__stack_chk_guard)($gp) lw $1, 0($3) sw $1, 56($sp) sw $4...
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
...2 > .type _Z5sum_iiz, at function > .set nomips16 # @_Z5sum_iiz > .ent _Z5sum_iiz > _Z5sum_iiz: > .cfi_startproc > .frame $sp,64,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -64 > $tmp2: > .cfi_def_cfa_offset 64 > sw $ra, 60($sp) # 4-byte Folded Spill > $tmp3: > .cfi_offset 31, -4 > addu $gp, $2, $25 > sw $7, 76($sp) > sw $6, 72($sp) > sw $5, 68($sp) > lw $3, %got(__stack_ch...
2016 Oct 15
3
How to remove memcpy
...i1 false) %1 = bitcast [10 x [10 x float]]* %b to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* bitcast ([10 x [10 x float]]* @main.b to i8*), i32 400, i32 4, i1 false) store i32 0, i32* %sum, align 4 *Assembly File Snip:* # BB#0: # %entry lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -1664 sw $ra, 1660($sp) # 4-byte Folded Spill sw $fp, 1656($sp) # 4-byte Folded Spill sw $17, 1652($sp) # 4-byte Folded Spill sw $16, 1648($sp) # 4-byte Folded Spill move $fp, $sp addu $17, $2, $25 lw $1, %got($main.a)...
2013 Feb 19
0
[LLVMdev] Is va_arg correct on Mips backend?
Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my
2013 Sep 02
0
[LLVMdev] .globl
...oes not emit), then the program will > run very slow if compiled in -fPIC and linked as C++. It seems to be > stuck in the loader (probably doing dynamic binding over and over again). This might or might not be related, but I notice that for the attached testcase, LLVM emits: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -32 $tmp2: .cfi_def_cfa_offset 32 sw $ra, 28($sp) # 4-byte Folded Spill sw $18, 24($sp) # 4-byte Folded Spill sw $17, 20($sp) # 4-byte Folded Spill sw $16, 16($sp) # 4-byte Folded Spill $tmp3: .cfi_offs...
2013 Feb 19
2
[LLVMdev] Is va_arg correct on Mips backend?
I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug. //ch8_3.cpp #include <stdarg.h> int sum_i(int amount, ...) { int i = 0; int val = 0; int sum = 0; va_list vl; va_start(vl, amount); for (i = 0; i < amount; i++) { val = va_arg(vl, int); sum += val; } va_end(vl);
2013 Feb 04
2
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...section .mdebug.abi32 .previous .file "helloworld.ll" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .frame $sp,24,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addu $gp, $2, $25 lw $1, %got($str)($gp) lw $25, %call16(puts)($gp) jalr $25 addiu $4, $1, %lo($str) addiu $2, $zero, 0 lw $ra, 20($sp) # 4-byte Folded Reload jr $ra addiu $sp, $...
2013 Aug 29
2
[LLVMdev] .globl
I need to be able to emit .globl for the soft float routines used by mips16. The routines are called but there is no .globl definition for them. How can I do this? Background: I have a strange issue that I encountered with mips16 hard float. Part of mips16 hard float is to emit calls to runtime routines with the same signature as usual soft float routines, except that they are implemented
2012 Aug 30
1
[LLVMdev] PHI
...ement. # Machine code for function main: Post SSA Frame Objects: fi#0: size=4, align=4, at location [SP-8] fi#1: size=4, align=4, at location [SP-12] fi#2: size=4, align=4, at location [SP-4] Function Live Outs: %V0 BB#0: derived from LLVM BB %entry %V0<def> = LiRxImmX16 <es:_gp_disp>[TF=5] SaveRaF16 32 %V1<def> = AddiuRxPcImmX16 <es:_gp_disp>[TF=6] %V0<def> = SllX16 %V0<kill>, 16 %S0<def> = AdduRxRyRz16 %V1<kill>, %V0<kill> %V0<def> = LiRxImmX16 0 SwRxRyOffMemX16 %V0, %SP, 24; mem:ST4[%retval]...
2015 Nov 21
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
...the `MipsTargetInfo`. Sure we can implement each of these methods somewhere in the `InputSectionBase` class under `if (MIPS)` statements. Any opinions about the best method / approach? == Q2 R_MIPS_HI16 and R_MIPS_LO16 relocations perform a special calculation if a target symbol's name is `_gp_disp` [2]. AFAIK now in the target `relocateOne` method there is no chance to get the traget symbol name. Is it okay to pass the target symbol index and provide `MipsTargetInfo` access to the symbol table of the processing input file? [1] ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf page...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...nomips16 # @main > .ent main > main: > .frame $sp,24,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addu $gp, $2, $25 > lw $1, %got($str)($gp) > lw $25, %call16(puts)($gp) > jalr $25 >...
2015 Nov 22
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
On Sun, Nov 22, 2015 at 1:28 AM, Rui Ueyama <ruiu at google.com> wrote: > I'm not sure if I understand the semantics of HI16 and LO16 relocations. If > my understanding is correct, a pair of HI16 and LO16 represents an addend > AHL. AHL is computed by (AHI<<16) | (ALO&0xFFFF). Can't we apply HI16 and > LO16 relocations separately and produce the same relocation
2016 Jan 12
2
greendragon build noisy due to mmap_stress.cc
...o *add*: llvm-revision.src/llvm/trunk/test/Transforms/FunctionImport/Inputs/funcimport_alias.ll o *add*: llvm-revision.src/llvm/trunk/test/Transforms/FunctionImport/funcimport_alias.ll * Commit *257492* by *atanasyan:* [ELF][MIPS] Do not create dynamic relocations against _gp_disp symbol MIPS _gp_disp designates offset between start of function and gp pointer into GOT therefore any relocations against it do not require dynamic relocation. o *edit*: llvm-revision.src/lld/trunk/ELF/Writer.cpp o *edit*: llvm-revision.src/lld/trunk/test/ELF/mips-gp-...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
On Mon, Feb 4, 2013 at 1:09 PM, <nkavv at physics.auth.gr> wrote: > Hi Justin, > > > Has anyone had similar problems with the NVPTX backend? Shouldn't this >>> code be linked to the AsmPrinter library for NVPTX (already)? >>> >> >> What do you mean by "doesn't work"? The AsmPrinter library really houses >> the MCInst