Displaying 2 results from an estimated 2 matches for "_fneg_rr".
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
.... You can use multiclasses :
multiclass Inst< node op, string opc> {
def _rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1,
GPR32:$src2),
"!strcat(opc, " $dst, $src1, $src2")",
[(set $dst, (op GPR32:$src1, GPR32:$src2))]>;
def _fneg_rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1,
GPR32:$src2),
"!strcat(opc, " $dst, -$src1, $src2")",
[(set $dst, (op (fneg_su GPR32:$src1), GPR32:$src2)))]>;
}
> I expect I can
> define a PatFrag:
>
> def fneg_su : PatFrag<(ops...
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
I've been unable to come up with the TableGen recipe to match a
negated operand. My target asm syntax allows the following transform:
FNEG r8, r5
MUL r6, r8, r9
to
MUL r6, -r5, r9
Is there a Pattern<> syntax that would allow matching *any* opcode (or
even some subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops