Displaying 3 results from an estimated 3 matches for "_addvsi3".
2007 Oct 08
2
[LLVMdev] Can't bootstrap llvm-gcc-4.0 for x84_64
...-I/llvm-project.modified/llvm-gcc-4.0/trunk/gcc/.
-I/llvm-project.modified/llvm-gcc-4.0/trunk/gcc/../include
-I/llvm-project.modified/llvm-gcc-4.0/trunk/gcc/../libcpp/include
-I/llvm-project.modified/llvm/trunk/include
-I/ptmp/dag/build.llvm.modified.debug/x86_64-unknown-linux-gnu/include
-DL_addvsi3 -c /llvm-project.modified/llvm-gcc-4.0/trunk/gcc/libgcc2.c -o
libgcc/./_addvsi3.o
[x86_64-mod-dbg]: /tmp/ccxekXCc.s: Assembler messages:
[x86_64-mod-dbg]: /tmp/ccxekXCc.s:36: Error: `(%esi,%edi)' is not a valid 64
bit base/index expression
I also see warnings like this:
[x86_64-mod-dbg]: ./...
2008 Jun 06
3
[LLVMdev] Variable length condition code for SETCC and SELECT?
...ice feature in the CellSPU architecture is the selb instruction
that directly corresponds to SELECT. Again, though, if SETCC is i32,
then SELECT has to be i32; if SETCC is i16, then SELECT has to be i16, etc.
Currently, I've got what looks to be a promotion problem showing up when
compiling _addvsi3.c during the libgcc2 phase of llvm-gcc. The optimized
selection DAG is show below:
Optimized lowered selection DAG:
SelectionDAG has 20 nodes:
0x14ffca0: ch = EntryToken
0x14ffca0: <multiple use>
0x1500710: i32 = Register #1025
0x1500770: i32,ch = CopyFromReg 0x14ffca0, 0x15007...
2007 Oct 08
0
[LLVMdev] Can't bootstrap llvm-gcc-4.0 for x84_64
...dified/llvm-gcc-4.0/trunk/gcc/.
> -I/llvm-project.modified/llvm-gcc-4.0/trunk/gcc/../include
> -I/llvm-project.modified/llvm-gcc-4.0/trunk/gcc/../libcpp/include
> -I/llvm-project.modified/llvm/trunk/include
> -I/ptmp/dag/build.llvm.modified.debug/x86_64-unknown-linux-gnu/include
> -DL_addvsi3 -c /llvm-project.modified/llvm-gcc-4.0/trunk/gcc/
> libgcc2.c -o
> libgcc/./_addvsi3.o
> [x86_64-mod-dbg]: /tmp/ccxekXCc.s: Assembler messages:
> [x86_64-mod-dbg]: /tmp/ccxekXCc.s:36: Error: `(%esi,%edi)' is not a
> valid 64
> bit base/index expression
Looks like llvm is g...