Displaying 2 results from an estimated 2 matches for "__size_".
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2017 Oct 09
4
{ARM} IfConversion does not detect BX instruction as a branch
...;, 255, pred:14, pred:%noreg, %CPSR<imp-def>;
> Bcc <BB#9>, pred:0, pred:%CPSR<kill>;
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg; mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg; mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRBi12 %R6, %R7<kill>, 0, pred:14,...
2017 Oct 11
2
{ARM} IfConversion does not detect BX instruction as a branch
...ed:%noreg, %CPSR<imp-def>;
> Bcc <BB#9>, pred:0, pred:%CPSR<kill>;
>
>
> BB#8:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRi12 %R6, %R7<kill>, 4, pred:14, pred:%noreg;
> mem:ST4[%__size_.i3.i.i.i.i]
> %R6<def> = LDRrs %R4, %R6<kill>, 16386, pred:14, pred:%noreg;
> mem:LD4[%0]
> BX %R6<kill>
>
> BB#9:
> Live Ins: %LR %R0 %R1 %R2 %R4 %R5 %R6 %R7 %R8 %R9 %R10 %R12
> Predecessors according to CFG: BB#7
> STRBi12 %R6, %R7<kill&...