search for: __io_apic_write

...entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) + = raw ? __io_apic_write : io_apic_write; + union entry_union eu = {{0, 0}}; + + eu.entry = e; + (*write)(apic, 0x11 + 2*pin, eu.w2); + (*write)(apic, 0x10 + 2*pin, eu.w1); +} + +static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + unsigned long flags; + spin_lock_...

...entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) + = raw ? __io_apic_write : io_apic_write; + union entry_union eu = {{0, 0}}; + + eu.entry = e; + (*write)(apic, 0x11 + 2*pin, eu.w2); + (*write)(apic, 0x10 + 2*pin, eu.w1); +} + +static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + unsigned long flags; + spin_lock_...

1: IOMMU: properly check whether interrupt remapping is enabled 2: AMD IOMMU: only disable when certain IVRS consistency checks fail 3: VT-d: deal with 5500/5520/X58 errata Patch 1 and 2 are version 2 of a previously submitted, then withdrawn patch following up after XSA-36. Patch 3 is version 3 of a patch previously sent by Malcolm and Andrew. Signed-off-by: Jan Beulich

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine