Displaying 20 results from an estimated 2460 matches for "__init".
2013 Jul 25
2
[PATCH V2 4/4] x86: correctly detect hypervisor
...lude <asm/processor.h>
#include <asm/hypervisor.h>
-/*
- * Hypervisor detect order. This is specified explicitly here because
- * some hypervisors might implement compatibility modes for other
- * hypervisors and therefore need to be detected in specific sequence.
- */
static const __initconst struct hypervisor_x86 * const hypervisors[] =
{
#ifdef CONFIG_XEN_PVHVM
@@ -49,15 +44,19 @@ static inline void __init
detect_hypervisor_vendor(void)
{
const struct hypervisor_x86 *h, * const *p;
+ uint32_t pri, max_pri = 0;
for (p = hypervisors; p < hypervisors + ARRAY_SIZE(hyperv...
2013 Jul 25
2
[PATCH V2 4/4] x86: correctly detect hypervisor
...lude <asm/processor.h>
#include <asm/hypervisor.h>
-/*
- * Hypervisor detect order. This is specified explicitly here because
- * some hypervisors might implement compatibility modes for other
- * hypervisors and therefore need to be detected in specific sequence.
- */
static const __initconst struct hypervisor_x86 * const hypervisors[] =
{
#ifdef CONFIG_XEN_PVHVM
@@ -49,15 +44,19 @@ static inline void __init
detect_hypervisor_vendor(void)
{
const struct hypervisor_x86 *h, * const *p;
+ uint32_t pri, max_pri = 0;
for (p = hypervisors; p < hypervisors + ARRAY_SIZE(hyperv...
2013 Jul 25
2
[PATCH V2 4/4] x86: correctly detect hypervisor
...lude <asm/processor.h>
#include <asm/hypervisor.h>
-/*
- * Hypervisor detect order. This is specified explicitly here because
- * some hypervisors might implement compatibility modes for other
- * hypervisors and therefore need to be detected in specific sequence.
- */
static const __initconst struct hypervisor_x86 * const hypervisors[] =
{
#ifdef CONFIG_XEN_PVHVM
@@ -49,15 +44,19 @@ static inline void __init
detect_hypervisor_vendor(void)
{
const struct hypervisor_x86 *h, * const *p;
+ uint32_t pri, max_pri = 0;
for (p = hypervisors; p < hypervisors + ARRAY_SIZE(hyperv...
2007 Apr 18
0
[PATCH 2/5] Interrupts subarch cleanup.patch
...quot;, NULL, NULL };
+static struct irqaction fpu_irq = {
+ .handler = math_error_irq,
+ .name = "fpu"
+};
+
+/*
+ * Most legacy systems want to cascade IRQ2 to slave PIC
+ */
+static struct irqaction cascade_action = {
+ .handler = no_action,
+ .name = "cascade",
+};
void __init init_ISA_irqs (void)
{
@@ -382,9 +393,6 @@ void __init native_init_IRQ(void)
{
int i;
- /* all the set up before the call gates are initialised */
- pre_intr_init_hook();
-
/*
* Cover the whole vector space, no vector can escape
* us. (some of these will be overridden and become
@@ -3...
2007 Apr 18
0
[PATCH 2/5] Interrupts subarch cleanup.patch
...quot;, NULL, NULL };
+static struct irqaction fpu_irq = {
+ .handler = math_error_irq,
+ .name = "fpu"
+};
+
+/*
+ * Most legacy systems want to cascade IRQ2 to slave PIC
+ */
+static struct irqaction cascade_action = {
+ .handler = no_action,
+ .name = "cascade",
+};
void __init init_ISA_irqs (void)
{
@@ -382,9 +393,6 @@ void __init native_init_IRQ(void)
{
int i;
- /* all the set up before the call gates are initialised */
- pre_intr_init_hook();
-
/*
* Cover the whole vector space, no vector can escape
* us. (some of these will be overridden and become
@@ -3...
2020 Apr 28
0
[PATCH v3 43/75] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
...| 3 ++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h
index 6f61bb93366a..af3e58aa1603 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -48,6 +48,7 @@ int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size);
void __init mem_encrypt_init(void);
void __init mem_encrypt_free_decrypted_mem(void);
+void __init sev_es_init_vc_handling(void);
bool sme_active(void);
bool sev_active(void);
bool sev_es_active(void);
@@ -71,6 +72,7 @@ sta...
2013 May 02
5
[PATCH] x86: allow Dom0 read-only access to IO-APICs
...the above described BIOS/ACPI behavior, and is expected to
also deal with a boot time crash of pv-ops Linux upon encountering the
same kind of system.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/domain_build.c
+++ b/xen/arch/x86/domain_build.c
@@ -1114,7 +1114,7 @@ int __init construct_dom0(
for ( i = 0; i < nr_ioapics; i++ )
{
mfn = paddr_to_pfn(mp_ioapics[i].mpc_apicaddr);
- if ( smp_found_config )
+ if ( !rangeset_contains_singleton(mmio_ro_ranges, mfn) )
rc |= iomem_deny_access(dom0, mfn, mfn);
}
--- a/xen/arch...
2020 Feb 12
5
[PATCH 0/5] x86/vmware: Steal time accounting support
...d
on steal clock. The steal clock is a per CPU structure in
a shared memory between hypervisor and guest, initialized
by each CPU through hypercall. Steal clock is got updated
by the hypervisor and read by the guest.
The patchset consists of 5 items:
1. x86/vmware: Make vmware_select_hypercall() __init
Minor clean up.
2. x86/vmware: Remove vmware_sched_clock_setup()
Preparation for the main patch.
3. x86/vmware: Steal time clock for VMware guest
Core steal time support functionality.
4. x86/vmware: Enable steal time accounting
Support for steal time accounting used by update_rq_clock().
5. x8...
2013 Jul 10
2
[PATCH] x86/HVM: key handler registration functions can be __init
This applies to both SVM and VMX.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -310,7 +310,7 @@ static struct keyhandler vmcb_dump_keyha
.desc = "dump AMD-V VMCBs"
};
-void setup_vmcb_dump(void)
+void __init setup_vmcb_dump(void)
{
register_keyhandler(''v'', &vmcb_dump_keyhandler);
}
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -1492,7 +1492,7 @@ static struct keyhandler vmcs_dump_keyha
.desc = "dump Intel''s VMCS"
};
-void...
2020 Sep 07
0
[PATCH v7 41/72] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
...| 3 ++
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h
index 4e72b73a9cb5..c9f5df0a1c10 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -49,6 +49,7 @@ void __init mem_encrypt_free_decrypted_mem(void);
/* Architecture __weak replacement functions */
void __init mem_encrypt_init(void);
+void __init sev_es_init_vc_handling(void);
bool sme_active(void);
bool sev_active(void);
bool sev_es_active(void);
@@ -72,6 +73,7 @@ static inline void __init sme_early_...
2013 Sep 12
3
[PATCH 1/1 V3] x86/AMD-Vi: Add additional check for invalid special->handle
...changed, 47 insertions(+), 13 deletions(-)
diff --git a/xen/drivers/passthrough/amd/iommu_acpi.c b/xen/drivers/passthrough/amd/iommu_acpi.c
index 89b359c..0e63e35 100644
--- a/xen/drivers/passthrough/amd/iommu_acpi.c
+++ b/xen/drivers/passthrough/amd/iommu_acpi.c
@@ -664,19 +664,46 @@ static void __init parse_ivrs_hpet(char *str)
ASSERT(*s == ''['');
id = simple_strtoul(s + 1, &s, 0);
- if ( id != (typeof(hpet_sbdf.id))id || *s != '']'' || *++s != ''='' )
+ if ( (*s != '']'') || (*++s != ''='') )...
2007 Apr 18
2
[PATCH 1/5] Skip timer works.patch
...time, and the 4 timer
IRQs have not yet been delivered.
In addition, it is entirely possible, though improbable, that this bug
could surface on real hardware which picks a particularly bad time to enter
SMM mode, causing a long latency during one of the timer IRQs.
While here, make check_timer be __init.
Signed-off-by: Zachary Amsden <zach@vmware.com>
===================================================================
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -603,8 +603,6 @@ and is between 256 and 4096 characters.
hugepages= [HW,IA-32,IA-6...
2007 Apr 18
2
[PATCH 1/5] Skip timer works.patch
...time, and the 4 timer
IRQs have not yet been delivered.
In addition, it is entirely possible, though improbable, that this bug
could surface on real hardware which picks a particularly bad time to enter
SMM mode, causing a long latency during one of the timer IRQs.
While here, make check_timer be __init.
Signed-off-by: Zachary Amsden <zach@vmware.com>
===================================================================
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -603,8 +603,6 @@ and is between 256 and 4096 characters.
hugepages= [HW,IA-32,IA-6...
2007 Apr 18
4
[patch 0/4] Clean up asm/bugs.h, identify_cpu() and update COMPAT_VDSO
Hi Andi,
Four patches:
- clean up asm/bugs.h, by moving all the C code into its own C file
- split identify_cpu() into boot and secondary variants, so that
boot-time setup functions can be marked __init
- repost of the COMPAT_VDSO patches with a bit more robustness from
unknown DT_tags, and functions marked __init, since all this is
boot-time only setup.
Thanks,
J
--
2007 Apr 18
4
[patch 0/4] Clean up asm/bugs.h, identify_cpu() and update COMPAT_VDSO
Hi Andi,
Four patches:
- clean up asm/bugs.h, by moving all the C code into its own C file
- split identify_cpu() into boot and secondary variants, so that
boot-time setup functions can be marked __init
- repost of the COMPAT_VDSO patches with a bit more robustness from
unknown DT_tags, and functions marked __init, since all this is
boot-time only setup.
Thanks,
J
--
2017 Nov 17
0
[RFC PATCH v2 4/5] ACPI/IORT: Support paravirtualized IOMMU
...FIG_ARM_SMMU_V3);
case ACPI_IORT_NODE_SMMU:
return IS_BUILTIN(CONFIG_ARM_SMMU);
+ case ACPI_IORT_NODE_PARAVIRT:
+ return IS_BUILTIN(CONFIG_VIRTIO_IOMMU);
default:
pr_warn("IORT node type %u does not describe an SMMU\n", type);
return false;
@@ -1062,6 +1065,48 @@ static bool __init arm_smmu_is_coherent(struct acpi_iort_node *node)
return smmu->flags & ACPI_IORT_SMMU_COHERENT_WALK;
}
+static int __init paravirt_count_resources(struct acpi_iort_node *node)
+{
+ struct acpi_iort_pviommu *pviommu;
+
+ pviommu = (struct acpi_iort_pviommu *)node->node_data;
+
+ /* Me...
2020 Feb 11
0
[PATCH 35/62] x86/sev-es: Setup per-cpu GHCBs for the runtime handler
...| 3 +++
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h
index 6f61bb93366a..d48e7be9bb49 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -48,6 +48,7 @@ int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size);
void __init mem_encrypt_init(void);
void __init mem_encrypt_free_decrypted_mem(void);
+void __init encrypted_state_init_ghcbs(void);
bool sme_active(void);
bool sev_active(void);
bool sev_es_active(void);
@@ -71,6 +72,7 @@...
2017 Nov 09
4
[PATCH v2 0/5] x86/xen: support booting PVH guest via standard boot path
Booting a Xen PVH guest requires a special boot entry as it is
mandatory to setup some Xen-specific interfaces rather early. When grub
or OVMF are used as boot loaders, however, those will fill the boot
parameters in zeropage and there is no longer a need to do something
PVH specific in the early boot path.
This patch series adds support for that scenario by identifying PVH
environment and doing
2017 Nov 09
4
[PATCH v2 0/5] x86/xen: support booting PVH guest via standard boot path
Booting a Xen PVH guest requires a special boot entry as it is
mandatory to setup some Xen-specific interfaces rather early. When grub
or OVMF are used as boot loaders, however, those will fill the boot
parameters in zeropage and there is no longer a need to do something
PVH specific in the early boot path.
This patch series adds support for that scenario by identifying PVH
environment and doing
2011 Dec 12
0
[PATCH 1/4] ACPI: eliminate duplicate MADT parsing and unused SBF definitions
...table_lsapic);
+ nbr_cpus * sizeof(*lsapic);
madt->header.checksum = -acpi_tb_checksum((u8*)madt,
madt->header.length);
return;
--- a/xen/arch/ia64/xen/dom_fw_dom0.c
+++ b/xen/arch/ia64/xen/dom_fw_dom0.c
@@ -53,11 +53,11 @@ static u32 lsapic_nbr;
static int __init
acpi_update_lsapic(struct acpi_subtable_header * header, const unsigned long end)
{
- struct acpi_table_lsapic *lsapic;
+ struct acpi_madt_local_sapic *lsapic =
+ container_of(header, struct acpi_madt_local_sapic, header);
int enable;
- lsapic = (struct acpi_table_lsapic *)header;
- if (!lsa...