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2024 Oct 08
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Question: Is CAREFUL_ALIGNMENT=1 needed for rsync on RISC-V
...rsync on RISC-V machines. I notice that the developers of
rsync seem to assume that only x86 CPUs can handle memory misalignments:
```c
/* We know that the x86 can handle misalignment and has the same
?* byte order (LSB-first) as the 32-bit numbers we transmit. */
#if defined __i386__ || defined __i486__ || defined __i586__ || defined
__i686__ || __amd64
#define CAREFUL_ALIGNMENT 0
#endif
#ifndef CAREFUL_ALIGNMENT
#define CAREFUL_ALIGNMENT 1
#endif
```
Thus, when copying 4-bit integers (just an example), rsync uses direct
copies on x86:
```c
static inline uint32
IVALu(const uchar *buf, int po...