Displaying 20 results from an estimated 24 matches for "__fp16".
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__be16
2014 Jun 19
2
[LLVMdev] __fp16 suport in llvm back-end
Hi, all:
I am trying to test half float point support in llvm, I found clang can generate bitcode for __fp16, while llc can't generate code for it, the error message is like this
LLVM ERROR: Cannot select: 0x26a68e0: i16 = fp32_to_fp16 0x26a67d8 [ORD=2] [ID=4]
0x26a67d8: f32,ch = CopyFromReg 0x2693060, 0x26a66d0 [ORD=2] [ID=3]
0x26a66d0: f32 = Register %vreg1 [ID=1]
In function: test
Anyone kn...
2014 Jul 14
5
[LLVMdev] RFC: Do we still need @llvm.convert.to.fp16 and the reverse?
...e actually are instructions acting on it. But it
adds the usual overheads of supporting bitcasts and loads/stores.
3. Targets with vector f16 conversion would similarly need to legalize
the type (and in this case would probably need argument-passing
support too, since Clang forbids passing a direct __fp16 but not a
vector).
I think it would be a worthwhile change, but want to make sure backend
owners with an interest in f16 don't object to the direction. That'd
seem to be: AArch64, ARM, NVPTX, R600 and X86.
Cheers.
Tim.
[1] I think this is an orthogonal issue to whether __fp16 is a
stora...
2019 Dec 10
2
TypePromoteFloat loses intermediate rounding operations
For the following C code
__fp16 x, y, z, w;
void foo() {
x = y + z;
x = x + w;
}
clang produces IR that extends each operand to float and then truncates to
half before assigning to x. Like this
define dso_local void @foo() #0 !dbg !18 {
%1 = load half, half* @y, align 2, !dbg !21
%2 = fpext half %1 to float, !dbg !21
%3 = load...
2019 Dec 10
2
TypePromoteFloat loses intermediate rounding operations
...> *To:* llvm-dev <llvm-dev at lists.llvm.org>; Eli Friedman <
> efriedma at quicinc.com>; Tim Northover <t.p.northover at gmail.com>
> *Subject:* [EXT] TypePromoteFloat loses intermediate rounding operations
>
>
>
> For the following C code
>
>
>
> __fp16 x, y, z, w;
>
>
>
> void foo() {
>
> x = y + z;
>
> x = x + w;
>
> }
>
>
>
> clang produces IR that extends each operand to float and then truncates to
> half before assigning to x. Like this
>
>
>
> define dso_local void @foo() #0 !dbg !18 {...
2017 Dec 04
2
[RFC] Half-Precision Support in the Arm Backends
Hi,
I am working on C/C++ language support for the Armv8.2-A half-precision
instructions. I've added support for _Float16 as a new source language type to
Clang. _Float16 is a C11 extension type for which arithmetic is well defined, as
opposed to e.g. __fp16 which is a storage-only type. I then fixed up the
AArch64 backend, which was mostly straightforward: this involved making
operations on f16 legal when FullFP16 is supported, thus avoiding promotions to
f32. This enables generation of AArch64 FP16 instruction from C/C++. For
AArch64, this work is fi...
2017 Nov 14
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
I’ve started running an ABI test suite with global isel on AArch64, and while it hasn’t found any ABI issues it has hit an assertion in clang when using the __fp16 type. Here’s a reproducer:
__fp16 pass_f16(__fp16 p) {
return p;
}
$ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
clang-6.0: /work/llvm/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp:446: stati...
2019 Apr 12
5
LLVM 7.1.0-final has been tagged
Hi,
I've just tagged LLVM 7.1.0-final. Testers, please upload the final binaries.
Thanks,
Tom
2017 Nov 14
6
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...tannard <oliver.stannard at arm.com <mailto:oliver.stannard at arm.com>> wrote:
>>
>> Hi Quentin,
>>
>> I’ve started running an ABI test suite with global isel on AArch64, and while it hasn’t found any ABI issues it has hit an assertion in clang when using the __fp16 type. Here’s a reproducer:
>>
>> __fp16 pass_f16(__fp16 p) {
>> return p;
>> }
>>
>> $ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
>> clang-6.0: /work...
2017 Nov 17
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...27 AM, Oliver Stannard <oliver.stannard at arm.com <mailto:oliver.stannard at arm.com>> wrote:
>
> Hi Quentin,
>
> I’ve started running an ABI test suite with global isel on AArch64, and while it hasn’t found any ABI issues it has hit an assertion in clang when using the __fp16 type. Here’s a reproducer:
>
> __fp16 pass_f16(__fp16 p) {
> return p;
> }
>
> $ /work/llvm/build/bin/clang --target=aarch64-arm-none-eabi -march=armv8-a -c test.c -O0 -mllvm -global-isel -mllvm -global-isel-abort=0
> clang-6.0: /work/llvm/llvm/lib/CodeGen/Globa...
2017 Nov 27
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...t;
> https://bugs.llvm.org/show_bug.cgi?id=35360 <https://bugs.llvm.org/show_bug.cgi?id=35360>
> https://bugs.llvm.org/show_bug.cgi?id=35361 <https://bugs.llvm.org/show_bug.cgi?id=35361>
>
> I also left the test suite running over the weekend in little-endian mode with the __fp16 type disabled, and it didn’t find any bugs there.
>
> Oliver
>
> From: qcolombet at apple.com [mailto:qcolombet at apple.com]
> Sent: 17 November 2017 17:28
> To: Oliver Stannard
> Cc: llvm-dev at lists.llvm.org; nd; Kristof Beyls
> Subject: Re: [llvm-dev] [GlobalISel][...
2014 Jul 14
2
[LLVMdev] RFC: Do we still need @llvm.convert.to.fp16 and the reverse?
...n it. But it
>> adds the usual overheads of supporting bitcasts and loads/stores.
>> 3. Targets with vector f16 conversion would similarly need to legalize
>> the type (and in this case would probably need argument-passing
>> support too, since Clang forbids passing a direct __fp16 but not a
>> vector).
>>
>> I think it would be a worthwhile change, but want to make sure backend
>> owners with an interest in f16 don't object to the direction. That'd
>> seem to be: AArch64, ARM, NVPTX, R600 and X86.
>>
>> Cheers.
>>
&g...
2019 Jan 22
4
_Float16 support
...pports _Float16 for target architectures that don't have direct support for 16-bit floating point arithmetic.
The current clang language extensions documentation says, "If half-precision instructions are unavailable, values will be promoted to single-precision, similar to the semantics of __fp16 except that the results will be stored in single-precision." This is somewhat vague (to me) as to what is meant by promotion of values, and the part about results being stored in single-precision isn't what actually happens.
Consider this example:
_Float16 x;
_Float16 f(_Float16 y, _Floa...
2016 Apr 14
2
Integer -> Floating point -> Integer cast optimizations
...tecture, we have chosen the 32-bit IEEE model provided by 'clang' for 'float' and 'double', but we have chosen the 64-bit IEEE model for 'long double'; other implementations are free to choose a different model. We also use IEEE 16-bit FP for 'half' aka '__fp16'. But IEEE also provides for 128-bit FP, 256-bit FP, and there are FP implementations that use 80-bits. In fact, 'clang' does not preclude an implementation choosing IEEE 754 16-bit Half-Precision as its representation for 'float'. This means 5-bits of exponent and 10-bits of...
2019 Jul 12
2
[cfe-dev] ARM float16 intrinsic test
...S="clang;lld"
-DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU;ARM;AArch64"
[arm.cpp]
#define vst4_lane_f16(__p0, __p1, __p2) __extension__ ({ \
float16x4x4_t __s1 = __p1; \
__builtin_neon_vst4_lane_v(__p0, __s1.val[0], __s1.val[1], __s1.val[2],
__s1.val[3], __p2, 8); \
})
typedef __fp16 float16_t;
typedef __attribute__((neon_vector_type(4))) float16_t float16x4_t;
typedef struct float16x4x4_t {
float16x4_t val[4];
} float16x4x4_t;
void test_vst4_lane_f16(float16_t * a, float16x4x4_t b) {
vst4_lane_f16(a, b, 3);
}
I tried:
$$COMP_ROOT/clang -cc1 -triple thumbv7s-apple-darwin -...
2016 Apr 15
2
Integer -> Floating point -> Integer cast optimizations
...tecture, we have chosen the 32-bit IEEE model provided by 'clang' for 'float' and 'double', but we have chosen the 64-bit IEEE model for 'long double'; other implementations are free to choose a different model. We also use IEEE 16-bit FP for 'half' aka '__fp16'. But IEEE also provides for 128-bit FP, 256-bit FP, and there are FP implementations that use 80-bits. In fact, 'clang' does not preclude an implementation choosing IEEE 754 16-bit Half-Precision as its representation for 'float'. This means 5-bits of exponent and 10-bits of...
2012 Nov 02
2
[LLVMdev] Half Float fp16 Native Support
...ve support for fp16 in llvm-3.1
i have already used the opencl patch for clang so the IR that is generated
is correct.
i tried to add some code so the the fp16 type is handled correctly but no
luck.
We have a target that has native fp16 units and tried to run a simple
program
int main ()
{
__fp16 a,b,c,d;
a= 1.1;
b=2.2;
c=3.3;
d = a + b + c;
return 0;
}
and when i try to call llc produces this error
LLVM ERROR: Cannot select: 0x234bab0: f16 = fadd 0x234b8b0, 0x234c2b0
[ORD=9] [ID=29]
0x234b8b0: f16 = fadd 0x2349970, 0x2349a70 [ORD=7] [ID=28]...
2017 Nov 13
3
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Hi Quentin,
My only remaining concern is around ABI compatibility.
The following commit seems to indicate that in the previous round of evaluation, we didn’t find an existing ABI compatibility issue:
http://llvm.org/viewvc/llvm-project?view=revision&revision=311388.
I haven’t looked into the details of this issue - so maybe I’m worried over nothing?
I’m wondering if since then on your side
2019 Jan 24
2
[cfe-dev] _Float16 support
...d need to make the calling convention explicit. But I guess that's a discussion for the other thread ;)
> The current clang language extensions documentation says, "If half-precision instructions are unavailable, values will be promoted to single-precision, similar to the semantics of __fp16 except that the results will be stored in single-precision." This is somewhat vague (to me) as to what is meant by promotion of values, and the part about results being stored in single-precision isn't what actually happens.
>
> Consider this example:
>
> _Float16 x;
> _Floa...
2019 Jan 24
4
[cfe-dev] _Float16 support
...ion explicit.
> But I guess that's a discussion for the other thread ;)
>
>> The current clang language extensions documentation says, "If
>> half-precision instructions are unavailable, values will be promoted
>> to single-precision, similar to the semantics of __fp16 except that
>> the results will be stored in single-precision." This is somewhat
>> vague (to me) as to what is meant by promotion of values, and the
>> part about results being stored in single-precision isn't what
>> actually happens.
>>
>> Conside...
2012 Aug 13
0
[LLVMdev] [cfe-dev] [RFC] Extending and improving Clang's undefined behavior checking
...ith a non-void return type, in C++ (in C, this is only UB if the caller uses the return value)
> - Overflow in conversion from floating point to smaller floating point or to integral type
> - Overflow in conversion from integral type to floating point (int128 to float, or when converting to __fp16)
> - Converting an out-of-range integer to an enumerated type
> - Floating-point arithmetic overflow
> - Pointer arithmetic which leaves the bounds which can be determined by llvm.objectsize
> - Pointer subtraction between pointers which can be determined to be in different objects...