search for: __fentry__

Displaying 20 results from an estimated 26 matches for "__fentry__".

2018 May 24
2
[PATCH v3 21/27] x86/ftrace: Adapt function tracing for PIE support
On Wed 2018-05-23 12:54:15, Thomas Garnier wrote: > When using -fPIE/PIC with function tracing, the compiler generates a > call through the GOT (call *__fentry__ at GOTPCREL). This instruction > takes 6 bytes instead of 5 on the usual relative call. > > If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop > so ftrace can handle the previous 5-bytes as before. > > Position Independent Executable (PIE) support will allow...
2018 May 24
2
[PATCH v3 21/27] x86/ftrace: Adapt function tracing for PIE support
On Wed 2018-05-23 12:54:15, Thomas Garnier wrote: > When using -fPIE/PIC with function tracing, the compiler generates a > call through the GOT (call *__fentry__ at GOTPCREL). This instruction > takes 6 bytes instead of 5 on the usual relative call. > > If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop > so ftrace can handle the previous 5-bytes as before. > > Position Independent Executable (PIE) support will allow...
2018 May 24
1
[PATCH v3 21/27] x86/ftrace: Adapt function tracing for PIE support
...mis.org> wrote: > On Thu, 24 May 2018 13:40:24 +0200 > Petr Mladek <pmladek at suse.com> wrote: > > On Wed 2018-05-23 12:54:15, Thomas Garnier wrote: > > > When using -fPIE/PIC with function tracing, the compiler generates a > > > call through the GOT (call *__fentry__ at GOTPCREL). This instruction > > > takes 6 bytes instead of 5 on the usual relative call. > > > > > > If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop > > > so ftrace can handle the previous 5-bytes as before. > > > > > &gt...
2017 Oct 05
2
[RFC v3 20/27] x86/ftrace: Adapt function tracing for PIE support
...Thu, Oct 5, 2017 at 6:06 AM, Steven Rostedt <rostedt at goodmis.org> wrote: > On Wed, 4 Oct 2017 14:19:56 -0700 > Thomas Garnier <thgarnie at google.com> wrote: > >> When using -fPIE/PIC with function tracing, the compiler generates a >> call through the GOT (call *__fentry__ at GOTPCREL). This instruction >> takes 6 bytes instead of 5 on the usual relative call. >> >> With this change, function tracing supports 6 bytes on traceable >> function and can still replace relative calls on the ftrace assembly >> functions. >> >> Posit...
2017 Oct 05
2
[RFC v3 20/27] x86/ftrace: Adapt function tracing for PIE support
...Thu, Oct 5, 2017 at 6:06 AM, Steven Rostedt <rostedt at goodmis.org> wrote: > On Wed, 4 Oct 2017 14:19:56 -0700 > Thomas Garnier <thgarnie at google.com> wrote: > >> When using -fPIE/PIC with function tracing, the compiler generates a >> call through the GOT (call *__fentry__ at GOTPCREL). This instruction >> takes 6 bytes instead of 5 on the usual relative call. >> >> With this change, function tracing supports 6 bytes on traceable >> function and can still replace relative calls on the ftrace assembly >> functions. >> >> Posit...
2017 Oct 04
1
[RFC v3 20/27] x86/ftrace: Adapt function tracing for PIE support
When using -fPIE/PIC with function tracing, the compiler generates a call through the GOT (call *__fentry__ at GOTPCREL). This instruction takes 6 bytes instead of 5 on the usual relative call. With this change, function tracing supports 6 bytes on traceable function and can still replace relative calls on the ftrace assembly functions. Position Independent Executable (PIE) support will allow to extend...
2018 May 24
0
[PATCH v3 21/27] x86/ftrace: Adapt function tracing for PIE support
On Thu, 24 May 2018 13:40:24 +0200 Petr Mladek <pmladek at suse.com> wrote: > On Wed 2018-05-23 12:54:15, Thomas Garnier wrote: > > When using -fPIE/PIC with function tracing, the compiler generates a > > call through the GOT (call *__fentry__ at GOTPCREL). This instruction > > takes 6 bytes instead of 5 on the usual relative call. > > > > If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop > > so ftrace can handle the previous 5-bytes as before. > > > > Position Independent Execu...
2018 May 23
0
[PATCH v3 21/27] x86/ftrace: Adapt function tracing for PIE support
When using -fPIE/PIC with function tracing, the compiler generates a call through the GOT (call *__fentry__ at GOTPCREL). This instruction takes 6 bytes instead of 5 on the usual relative call. If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop so ftrace can handle the previous 5-bytes as before. Position Independent Executable (PIE) support will allow to extended the KASLR randomi...
2018 Mar 13
0
[PATCH v2 21/27] x86/ftrace: Adapt function tracing for PIE support
When using -fPIE/PIC with function tracing, the compiler generates a call through the GOT (call *__fentry__ at GOTPCREL). This instruction takes 6 bytes instead of 5 on the usual relative call. If PIE is enabled, replace the 6th byte of the GOT call by a 1-byte nop so ftrace can handle the previous 5-bytes as before. Position Independent Executable (PIE) support will allow to extended the KASLR randomi...
2018 Feb 14
0
[inline-asm][asm-goto] Supporting "asm goto" in inline assembly
...n handling of instructions which might fault, as well as for runtime patching of instructions like the above. It's not always a nop vs. call alternative. It would be nice to have the compiler assist with that. We currently have code to trawl through all the built object files and find calls to __fentry__ so we can patch them in/out at runtime, for example. And we might considered doing the same for calls to the retpoline thunks. But I think we would be best served right now by considering that out of scope, and looking *only* at the part which is handled by 'asm goto'. -------------- nex...
2017 Feb 14
2
[PATCH v2 0/3] x86/vdso: Add Hyper-V TSC page clocksource support
..._hyperv_tsc_page are volatile we don't need READ_ONCE(), compilers are not allowed to merge accesses. The resulting code looks good to me: (gdb) disassemble read_hv_clock_tsc Dump of assembler code for function read_hv_clock_tsc: 0xffffffff8102ca60 <+0>: callq 0xffffffff816c7500 <__fentry__> 0xffffffff8102ca65 <+5>: mov 0xf67974(%rip),%rcx # 0xffffffff81f943e0 <tsc_pg> 0xffffffff8102ca6c <+12>: jmp 0xffffffff8102ca87 <read_hv_clock_tsc+39> 0xffffffff8102ca6e <+14>: lfence 0xffffffff8102ca71 <+17>: mov 0x8(%rcx),%r9...
2017 Feb 14
2
[PATCH v2 0/3] x86/vdso: Add Hyper-V TSC page clocksource support
..._hyperv_tsc_page are volatile we don't need READ_ONCE(), compilers are not allowed to merge accesses. The resulting code looks good to me: (gdb) disassemble read_hv_clock_tsc Dump of assembler code for function read_hv_clock_tsc: 0xffffffff8102ca60 <+0>: callq 0xffffffff816c7500 <__fentry__> 0xffffffff8102ca65 <+5>: mov 0xf67974(%rip),%rcx # 0xffffffff81f943e0 <tsc_pg> 0xffffffff8102ca6c <+12>: jmp 0xffffffff8102ca87 <read_hv_clock_tsc+39> 0xffffffff8102ca6e <+14>: lfence 0xffffffff8102ca71 <+17>: mov 0x8(%rcx),%r9...
2017 Oct 05
0
[RFC v3 20/27] x86/ftrace: Adapt function tracing for PIE support
On Wed, 4 Oct 2017 14:19:56 -0700 Thomas Garnier <thgarnie at google.com> wrote: > When using -fPIE/PIC with function tracing, the compiler generates a > call through the GOT (call *__fentry__ at GOTPCREL). This instruction > takes 6 bytes instead of 5 on the usual relative call. > > With this change, function tracing supports 6 bytes on traceable > function and can still replace relative calls on the ftrace assembly > functions. > > Position Independent Executable...
2017 Oct 05
0
[RFC v3 20/27] x86/ftrace: Adapt function tracing for PIE support
..., Steven Rostedt <rostedt at goodmis.org> wrote: > > On Wed, 4 Oct 2017 14:19:56 -0700 > > Thomas Garnier <thgarnie at google.com> wrote: > > > >> When using -fPIE/PIC with function tracing, the compiler generates a > >> call through the GOT (call *__fentry__ at GOTPCREL). This instruction > >> takes 6 bytes instead of 5 on the usual relative call. > >> > >> With this change, function tracing supports 6 bytes on traceable > >> function and can still replace relative calls on the ftrace assembly > >> functions...
2017 Feb 14
0
[PATCH v2 0/3] x86/vdso: Add Hyper-V TSC page clocksource support
...and it can observably screw up as a result. Also, Linux tries to avoid volatile variables, so please use READ_ONCE(). > > (gdb) disassemble read_hv_clock_tsc > Dump of assembler code for function read_hv_clock_tsc: > 0xffffffff8102ca60 <+0>: callq 0xffffffff816c7500 <__fentry__> > 0xffffffff8102ca65 <+5>: mov 0xf67974(%rip),%rcx # 0xffffffff81f943e0 <tsc_pg> > 0xffffffff8102ca6c <+12>: jmp 0xffffffff8102ca87 <read_hv_clock_tsc+39> > 0xffffffff8102ca6e <+14>: lfence > 0xffffffff8102ca71 <+17...
2017 Apr 04
1
[inline-asm][asm-goto] Supporting "asm goto" in inline assembly
On Tue, Apr 4, 2017 at 6:07 AM Yatsina, Marina via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Asm goto feature was introduces to GCC in order to optimize the support > for tracepoints in Linux kernel (it can be used for other things that do > nop patching). > > > > GCC documentation describes their motivating example here: > > >
2017 Feb 14
6
[PATCH v2 0/3] x86/vdso: Add Hyper-V TSC page clocksource support
Hi, while we're still waiting for a definitive ACK from Microsoft that the algorithm is good for SMP case (as we can't prevent the code in vdso from migrating between CPUs) I'd like to send v2 with some modifications to keep the discussion going. Changes since v1: - Document the TSC page reading protocol [Thomas Gleixner]. - Separate the TSC page reading code from
2017 Feb 14
6
[PATCH v2 0/3] x86/vdso: Add Hyper-V TSC page clocksource support
Hi, while we're still waiting for a definitive ACK from Microsoft that the algorithm is good for SMP case (as we can't prevent the code in vdso from migrating between CPUs) I'd like to send v2 with some modifications to keep the discussion going. Changes since v1: - Document the TSC page reading protocol [Thomas Gleixner]. - Separate the TSC page reading code from
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to