search for: __dummy__

...x)>> 2)) : __L2( _x)) -#define __L8(_x) (((_x) & 0x000000f0) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x)) -#define __L16(_x) (((_x) & 0x0000ff00) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x)) -#define LOG_2(_x) (((_x) & 0xffff0000) ? (16 + __L16((_x)>>16)) : __L16(_x)) - void __dummy__(void) { OFFSET(UREGS_sp, struct cpu_user_regs, sp); diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c index b6d1919..6dc832c 100644 --- a/xen/arch/x86/x86_64/asm-offsets.c +++ b/xen/arch/x86/x86_64/asm-offsets.c @@ -8,6 +8,7 @@ #include <xen/config.h> #...

Hi, This is the fifth version of this patch series. With the Versatile Express TC2, it''s possible to boot only with A7 or A15. If the user choose to boot with only A7, the CPU ID will start at 0x100. As Xen relies on it to set the logical ID and the GIC, it won''t be possible to use Xen with this use case. This patch series is divided in 3 parts: - Patch 1: prepare Xen

...1,6 +11,7 @@ #include <xen/bitops.h> #include <public/xen.h> #include <asm/current.h> +#include <asm/procinfo.h> #define DEFINE(_sym, _val) \ __asm__ __volatile__ ( "\n->" #_sym " %0 " #_val : : "i" (_val) ) @@ -62,6 +63,12 @@ void __dummy__(void) DEFINE(CPUINFO_sizeof, sizeof(struct cpu_info)); OFFSET(VCPU_arch_saved_context, struct vcpu, arch.saved_context); + + BLANK(); + DEFINE(PROCINFO_sizeof, sizeof(struct proc_info_list)); + OFFSET(PROCINFO_cpu_val, struct proc_info_list, cpu_val); + OFFSET(PROCINFO_cpu_mask, s...

...arch/x86/x86_32/asm-offsets.c =================================================================== --- 2007-03-19.orig/xen/arch/x86/x86_32/asm-offsets.c 2007-03-19 13:23:52.000000000 +0100 +++ 2007-03-19/xen/arch/x86/x86_32/asm-offsets.c 2007-03-27 11:16:21.000000000 +0200 @@ -107,21 +107,11 @@ void __dummy__(void) BLANK(); #if PERF_COUNTERS - OFFSET(PERFC_hypercalls, struct perfcounter, hypercalls); - OFFSET(PERFC_exceptions, struct perfcounter, exceptions); + DEFINE(PERFC_hypercalls, PERFC_hypercalls); + DEFINE(PERFC_exceptions, PERFC_exceptions); BLANK(); #endif - OFFSE...

...en/arch/x86/x86_64/asm-offsets.c =================================================================== --- 2007-08-08.orig/xen/arch/x86/x86_64/asm-offsets.c 2007-06-04 08:35:35.000000000 +0200 +++ 2007-08-08/xen/arch/x86/x86_64/asm-offsets.c 2007-08-08 11:37:08.000000000 +0200 @@ -71,6 +71,22 @@ void __dummy__(void) arch.guest_context.failsafe_callback_cs); OFFSET(VCPU_syscall_addr, struct vcpu, arch.guest_context.syscall_callback_eip); + OFFSET(VCPU_syscall32_addr, struct vcpu, arch.syscall32_callback_eip); + OFFSET(VCPU_syscall32_sel, struct vcpu, arch.syscall32_callb...

...sets.c 2006-10-04 15:11:03.000000000 +0200 @@ -7,6 +7,9 @@ #include <xen/config.h> #include <xen/perfc.h> #include <xen/sched.h> +#ifdef CONFIG_COMPAT +#include <compat/xen.h> +#endif #include <asm/fixmap.h> #include <asm/hardirq.h> @@ -95,9 +98,15 @@ void __dummy__(void) OFFSET(VMCB_tsc_offset, struct vmcb_struct, tsc_offset); BLANK(); - OFFSET(VCPUINFO_upcall_pending, vcpu_info_t, evtchn_upcall_pending); - OFFSET(VCPUINFO_upcall_mask, vcpu_info_t, evtchn_upcall_mask); + OFFSET(VCPUINFO_upcall_pending, struct vcpu_info, evtchn_upcall_pend...

The self_nmi() code cause''s an NMI to be triggered by sending an APIC message to the local processor. However, NMIs are blocked by the VMEXIT, until the next iret or VMENTER. Volume 3 Chapter 27 Section 1 of the Intel SDM states: An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes. As a result, as soon as the VMENTER happens, an immediate VMEXIT happens

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

Hello everyone, this is the fourth version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

Hello everyone, this is the very first version of the patch series that introduces ARMv7 with virtualization extensions support in Xen. The series allows Xen and Dom0 to boot on a Cortex-A15 based Versatile Express simulator. See the following announce email for more informations about what we are trying to achieve, as well as the original git history: See

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I