Displaying 2 results from an estimated 2 matches for "__c11_compare_exchange_weak".
2014 May 29
3
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
...o resolving
this, but it's still difficult to see a path from an IR-level "cmpxchg
weak" to optimal "atomicrmw lambda" support in LL/SC backends.
Given C like
void atomic_foo(int *addr) {
int oldval = *addr;
do {
newval = foo(oldval);
} while (__c11_compare_exchange_weak(addr, &oldval, newval));
The cmpxchg representation would be something like:
define void @atomic_foo(int *addr) {
entry:
%firstval = load i32* %addr
br label %loop
loop:
%oldval = phi i32 [%firstval, %entry], [%wrongval, %loop]
%newval = call i32 @f...
2014 May 29
4
[LLVMdev] Proposal: "load linked" and "store conditional" atomic instructions
Hi,
I've been looking at improving atomicrmw & cmpxchg code more,
particularly on architectures using the load-linked/store-conditional
model.
The summary is that current expansion for cmpxchg seems to happen too
late for LLVM to make meaningful use of the opportunities it provides.
I'd like to move it earlier and express it in terms of a first-class
pair of "load linked"