Displaying 2 results from an estimated 2 matches for "_0eevt__sm0".
2017 Dec 06
2
[AMDGPU] Strange results with different address spaces
...2 %add.i.i.i.i.i to i64
DIVERGENT: %8 = getelementptr i32, i32 addrspace(1)* %callable.coerce0, i64 %idxprom.i.i.i
DIVERGENT: %9 = load i32, i32 addrspace(1)* %8, align 4
DIVERGENT: %10 = getelementptr [16 x i32], [16 x i32] addrspace(3)* @"_ZN5pacxx2v213genericKernelIZL12test_barrieriPPcE3$_0EEvT__sm0", i32 0, i32 %6
DIVERGENT: store i32 %9, i32 addrspace(3)* %10, align 4
DIVERGENT: %11 = load i32, i32 addrspace(3)* %10, align 4
DIVERGENT: %12 = getelementptr i32, i32 addrspace(1)* %callable.coerce1, i64 %idxprom.i.i.i
DIVERGENT: store i32 %11, i32 addrspace(1)* %12, align 4
I’m also q...
2017 Dec 05
2
[AMDGPU] Strange results with different address spaces
> On Dec 5, 2017, at 13:53, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
>
>
>> On Dec 5, 2017, at 02:51, Haidl, Michael via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>>
>> Hi dev list,
>>
>> I am currently exploring the integration of AMDGPU/ROCm into the PACXX project and observing some