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...would work just as well. LLVM's register coalescer and allocator don't try to reschedule instructions, which seems to be required here. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130111/9dc4635f/attachment.html>

llvm-dev, I'm trying to get a better understanding of sub-registers. I'm seeing the code generator make an odd decision that I was hoping someone could point me in the right direction of explaining. The architecture is 68000, which has 8, 16, and 32 bit views of all of it's data registers. In order to zero extend you can load a big view with zero, and then copy into the small view.