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981017
2013 Nov 11
2
[LLVMdev] basic block missing after MachineInstr packetizing
Hi, all,
When I schedule machine instructions in a VLIW way and packetize them, a
problem is encountered, and I will show it use a simplified case as follows.
############ original instruction sequence
...
insn1
...
jump LBB0_xx
...
LBB0_xx:
...
############ expected instruction sequence after scheduling and packetizing
insn1; jump LBB0_xx
...
LBB0_xx:
...
############ generated instruction