search for: 96r

..., with debugging turned on: $llc bugpoint.reduced.simplified.bc -debug ... 208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34 Considering merging to VecRegs with %vreg34 in %vreg13 RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r LHS = %vreg13 [96r,112r...

...ts due to this identity copy in %bb.1, which is removed. When the copy is erased and the interval is updated (https://github.com/llvm/llvm-project/blob/523cc097fdafa1bb60373dcc70df7dfd31551f56/llvm/lib/CodeGen/RegisterCoalescer.cpp#L1871), the new live interval looks like this: %0 [16r,32B:2)[32B,96r:0)[96r,128B:1) 0 at 32B-phi 1 at 96r 2 at 16r L0000000000000003 [32B,80B:0) 0 at 32B-phi // sub0 This remaining [32B,80B:0) across %bb.1 is a fake phi-only segment. If I freshly recompute LiveIntervals, the subrange is empty as it should be. The verifier doesn't care about this, however it...

...b_0<def,read-undef> = ... 32B %vreg0:ssub_1<def> = ... 48B = %vreg0 64B = %vreg0:ssub_0 80B %vreg0 = ... 96B = %vreg0:ssub_1 will be represented as the following live range(s): Common LiveRange: [16r,32r)[32r,64r),[80r,96r) SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d) SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r) Patches/Changes: * Moves live range management code in the LiveInterval class to a new class LiveRange, move the previous LiveRange class (which was just a single interval...

...def> = ... > 48B = %vreg0 > 64B = %vreg0:ssub_0 > 80B %vreg0 = ... > 96B = %vreg0:ssub_1 > > will be represented as the following live range(s): > > Common LiveRange: [16r,32r)[32r,64r),[80r,96r) > SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d) > SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r) > > Patches/Changes: > * Moves live range management code in the LiveInterval class to a new > class LiveRange, move the previous LiveRang...

...= ... >> 48B = %vreg0 >> 64B = %vreg0:ssub_0 >> 80B %vreg0 = ... >> 96B = %vreg0:ssub_1 >> >> will be represented as the following live range(s): >> >> Common LiveRange: [16r,32r)[32r,64r),[80r,96r) >> SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d) >> SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r) >> >> Patches/Changes: >> * Moves live range management code in the LiveInterval class to a new >> class LiveRange, move the previous Live...

...352r:0) 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 register: %vreg16 +[32r,240r:0) 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 register: %vreg15 +[48r,160r:0) 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 register: %vreg14 +[64r,96r:0) 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 register: %vreg18 +[80r,128r:0) 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 register: %vreg19 +[96r,144r:0) 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 register: %vreg2...

...> = COPY %T1_Z<kill>; R600_TReg32:%vreg16 > register: %vreg16 +[32r,240r:0) > 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15 > register: %vreg15 +[48r,160r:0) > 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14 > register: %vreg14 +[64r,96r:0) > 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18 > register: %vreg18 +[80r,128r:0) > 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; > R600_Reg128:%vreg19 R600_TReg32:%vreg14 > register: %vreg19 +[96r,144r:0) > 112B%vreg2<def> = COPY %C1_Y; R60...

...= ... >> 48B = %vreg0 >> 64B = %vreg0:ssub_0 >> 80B %vreg0 = ... >> 96B = %vreg0:ssub_1 >> >> will be represented as the following live range(s): >> >> Common LiveRange: [16r,32r)[32r,64r),[80r,96r) >> SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d) >> SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r) >> >> Patches/Changes: >> * Moves live range management code in the LiveInterval class to a new >> class LiveRange, move the previous Liv...

.../tinycrypt/blob/master/lib/source/ecc_dh.c#L139 Thanks, Prathamesh -------------- next part -------------- PreferIndirect: 1 PreferIndirect: 1 PreferIndirect: 1 Computing live-in reg-units in ABI blocks. 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r %0 [48r,288r:0) 0 at 48r weigh...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...pers mailing list > > llvm-dev at lists.llvm.org > > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -------------- next part -------------- Computing live-in reg-units in ABI blocks. 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1...

...BG/0GXLJkCnrxOOY6dxUadEQr1///WD//o+9lcwySCeKMYBH6IfD60SDaWGP//C20a tP79DfmFLxc8ElmZ8pTEva13P5f6//+Km7oEcC+WPZtk5VYGPx9AyxM4TmdJ5UD//y/wr6D5 Yti3baLS9BgR3kWCwpByynGZ2Id7//b//9Su4MvyOELWa/GDB2rTRHqQykUHx8xHu4URWQz/ hd/+jlBa2iHzgUNb8zMYB0H3OhvDtHkCT/////+dmCY5FAznjzKIAFTPzo3QiomVk33AQMf8 qX2QAYQL+P////96r/rnnBFrESdWj2HEzoXlZnLkqXJeBJSU4vAZHprDLP/f/v+euRrQGCMx ofF/X8H1OKC/TOO2LPWrpeUO3I0O/v///0zWNUQ4jZYpBZ3NuckNTAx4mUzOHpYeLrQduYb2 eFwX/v8FCpNPxfSk2+bw83ufXsJlfY3umP+3Fvjxeo+1V0EulW9ToudvYxV/VS//////1xaf 4CKNgc13JeOsen8bM3HOgnGjIxaYXE8IP75bd9N/iVLRIhoJE0ZVf2EOler/X/ioyTStMN+L d9J/FPA/peSgsvGhJmjf+v9fV...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

...: %vreg0 +[64r,416r:0) 80B%vreg4<def> = MOV 1, 0, 0, 0, %vreg3, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg4 R600_TReg32:%vreg3 register: %vreg4 +[80r,112r:0) 96B%vreg5<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg5 register: %vreg5 +[96r,144r:0) 112B%vreg6<def> = ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5 register: %vreg6 +[112r,160r:0) 128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TRe...

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2