Displaying 20 results from an estimated 45 matches for "96b".
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2013 Aug 02
0
[LLVMdev] Missing optimization - constant parameter
...OV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
96B %RDI<def> = COPY %vreg2; GR64:%vreg2
112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
%RDI<imp-use,kill>
into
0B BB#0: derived from LLVM BB %entry
16B %vreg0<def> = MOV64rm %RIP, 1, %noreg,
<ga:@val>[TF=5],...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
For the little C test program where a constant is stored in memory and
also
used as a parameter:
#include <stdint.h>
uint64_t val, *p;
extern uint64_t xtr( uint64_t);
uint64_t caller() {
uint64_t x;
p = &val;
x = 12345123400L;
*p = x;
return xtr(x);
}
clang (3.2, 3.3 and svn) generates the following X86 code (at -O3):
caller:
movq
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
...0, %noreg, %vreg0;
> mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
> %RDI<imp-use,kill>
>
> into
>
> 0B BB#0: derived from LLVM BB %entry
> 16B %vreg0<def> = MOV64rm %RIP...
2019 Sep 06
2
[PATCH 1/1] log: do not print carriage return
...g terminated with carriage
return (\r) and new line (\n). While this is fine for terminals it may
have undesired effects when running from crond and logging to syslog
or similar.
I run ssh from cron on an recent linux host. Viewing logs with
journalctl I see:
Sep 06 16:50:01 linux CROND[152575]: [96B blob data]
Adding switch --all for unprintable characters it shows:
Sep 06 16:50:01 linux CROND[152575]: (root) CMDOUT (Warning: Permanently
added '10.52.33.217' (ED25519) to the list of known hosts.^M)
Note the control character ^M. Removing the carriage return fixes this.
Signed-off-b...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2
64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5
96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5
112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass:%vreg7 FPUaROUTMULRegisterClass:%vreg6
128B %vreg8<def> = FADD_A_oo...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
...9<def> = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
The MI move triggers liveness update, which first triggers SlotIndex
renumbering:
*** Renumbered SlotIndexes 24-56 ***
So my 48B becomes 56B, so after the upd...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...;kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
> The MI move triggers liveness update, which first triggers SlotIndex
> renumbering:
>
> *** Renumbered SlotIndexes 24-56...
2013 Aug 05
0
[LLVMdev] Missing optimization - constant parameter
...> mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> > 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> > 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
> > %RDI<imp-use,kill>
> >
> > into
> >
> > 0B BB#0: derived from LLVM BB %entry
> > 16B...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...; = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
The MI move triggers liveness update, which first triggers SlotIndex
renumbering:
*** Renumbered SlotIndexes 24-56 ***
So my 48B becomes 56B, so af...
2016 Dec 22
1
Spill hoisting on RAL: looking for some debugging ideas
...)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5)
0 at 16r 1 at 144B-phi 2 at 240B-phi
3 at 296r 4 at 416B-phi 5 at 472r
Merged to stack int: SS#0 [16r,592B:0) 0 at x
hoisted: 16r STbo %vreg19, <fi#0>
Second below:
Checking redundant spills for 0 at 16r in %vreg19
[16r,96B:0)[144B,240B:1)[296r,416B:2)[416B,456r:3)[472r,592B:4) 0 at 16r
1 at 144B-phi 2 at 296r 3 at 416B-phi 4 at 472r
Merged to stack int: SS#0 [16r,592B:0) 0 at x
hoisted: 16r STbo %vreg19, <fi#0>
Result just prior to rewriting:
20B STbo %vreg19, <fi#0>
24B S...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...COPY %D2<kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
> The MI move triggers liveness update, which first triggers SlotIndex
> renumbering:
>
> *** Renumbered SlotIndexes 24-56 ***
>...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...m LLVM BB %entry
16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>,...
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...; = COPY %D2<kill>; DoubleRegs:%vreg29
48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
IntRegs:%vreg37
In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
The MI move triggers liveness update, which first triggers SlotIndex
renumbering:
*** Renumbered SlotIndexes 24-56 ***
So my 48B becomes 56B, so af...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...DoubleRegs:%vreg29
>> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
>> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
>> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
>> IntRegs:%vreg37
>>
>> In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
>> The MI move triggers liveness update, which first triggers SlotIndex
>> renumbering:
>>
>> *** Ren...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...eg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...eg29
> >> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> >> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> >> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> >> IntRegs:%vreg37
> >>
> >> In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
> >> The MI move triggers liveness update, which first triggers SlotIndex
> >> renumbering:...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...0 in %0, $r1 in %1, $r2 in %2
0B bb.0.entry:
liveins: $r0, $r1, $r2
16B %2:tgpr = COPY $r2
32B %1:tgpr = COPY $r1
48B %0:tgpr = COPY $r0
64B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
80B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
96B $r0 = COPY %0:tgpr
112B $r1 = COPY %1:tgpr
128B $r2 = COPY %2:tgpr
144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit...
2018 Sep 11
2
linear-scan RA
...>
> 0B bb.0:
> successors: %bb.2(0x80000000); %bb.2(100.00%)
>
> 16B %0:gr32 = MOV32ri 42
> 32B JB_1 %bb.2, implicit undef $eflags
> 48B JMP_1 %bb.2
>
> 64B bb.1:
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 80B %1:gr32 = MOV32ri 17
> 96B JMP_1 %bb.3
>
> 112B bb.2:
> ; predecessors: %bb.0
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 128B NOOP implicit %0:gr32
> 144B %1:gr32 = COPY %0:gr32
> 160B JMP_1 %bb.3
>
> 176B bb.3:
> ; predecessors: %bb.1, %bb.2
>
> 192B NOOP im...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...;kill>; DoubleRegs:%vreg29
> 48B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28
> <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Needs to move above 28B
> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8]
> IntRegs:%vreg37
>
> In Hexagon %D1==%R0:R1 (double reg), %D2==%R2:R3 etc.
> The MI move triggers liveness update, which first triggers SlotIndex
> renumbering:
>
> *** Renumbered SlotIndexes 24-56...