search for: 960b

I am going to have to find a fix for this problem or I'm going to have to quit using iconnect. About one call in 10 or so, iconnect's gateway gives me an error (console output appended below). So upon receiving the error, which as a 4XX error means, "Fatal," asterisk gives up and drops the call. But not iconnect!! The phone at the other end starts ringing, and rings

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

...amp;): Assertion `!isAllocatable(interval.reg) && "Physregs shouldn't be live out!"' failed. in this case the loop is quite simple: 944B BB#8: derived from LLVM BB %for.inc6, ADDRESS TAKEN Live Ins: %CTR8 Predecessors according to CFG: BB#8 BB#3 960B BDNZ8 <BB#8>, %CTR8<imp-def>, %CTR8<imp-use,kill> Successors according to CFG: BB#8 BB#10 the preheader is: 240B BB#3: Predecessors according to CFG: BB#2 256B %vreg28<def> = LI 0; GPRC:%vreg28 272B %vreg30<de...

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the

...R600_Reg128:%vreg32 R600_Reg32:%vreg31 register: %vreg32 +[912r,944r:0) 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 register: %vreg34 +[928r,960r:0) 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 register: %vreg35 +[944r,976r:0) 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 register: %vreg35 replace range with [944r,960r:1) RESULT: [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35 register: %vreg36 +[97...

...g31 > register: %vreg32 +[912r,944r:0) > 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 > R600_Reg128:%vreg6 > register: %vreg34 +[928r,960r:0) > 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 > register: %vreg35 +[944r,976r:0) > 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 > R600_Reg32:%vreg34 > register: %vreg35 replace range with [944r,960r:1) RESULT: > [944r,960r:1)[960r,976r:0)  0 at 960r 1 at 944r > 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35...

...g128:%vreg6 > 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 > 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 > 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 > 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35 > 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5 > 1008B%vreg37<def&...

...eg32:%vreg31 R600_Reg128:%vreg6 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34 976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35 992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36 R600_Reg32:%vreg5 1008B%vreg37<def> = COPY %vre...