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Thanks for the work so far. A quick scan through the first NVC4 trace at hand, using upstream demmio, reveals at least 20 writes to the BLCG registers of PGRAPH and a few in PXBAR prior to altering the value of register 0x20200 (see below). We know that these are related to the clock gating you enable. Are you 110% sure that fiddling with 0x20200 bits without first setting these values can

This adds support for enabling automatic clockgating on nvidia GPUs for Fermi and later generations. This saves a little bit of power, bringing my fermi GPU's power consumption from ~28.3W on idle to ~27W, and my kepler's idle power consumption from ~23.6W to ~21.65W. Similar to how the nvidia driver seems to handle this, we enable clockgating for each engine that supports it after