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58530
2017 Jul 07
2
Unhandled reg/opcode register encoding VR2048 Error in backend
Hello,
I m working towards backend.
Here i need to define vector load and stores for 64 i32 elements. so in
x86instrinfo.td i wrote;
def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins
i32mem:$src),
"vmov_256B_rm\t{$src, $dst|$dst, $src}",
[(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32
addr:$src))))],